Datasheet

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor 161
Figure 5-1. ATD Block Diagram
V
SSA
ATD10B8C
Analog
MUX
Mode and
Successive
Approximation
Register (SAR)
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
and DAC
Sample & Hold
1
1
V
DDA
V
RL
V
RH
Sequence Complete
Interrupt
+
–
Comparator
Clock
Prescaler
Bus Clock ATD clock
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
ETRIG0
(See Device Overview
chapter for availability
ETRIG1
ETRIG2
ETRIG3
and connectivity)
Timing Control
ATDDIEN
ATDCTL1
PORTAD
Trigger
Mux