Datasheet

Appendix E Detailed Register Address Map
MC9S12XE-Family Reference Manual Rev. 1.25
1302 Freescale Semiconductor
0x0278 PT0AD1
R
PT0AD1
7
PT0AD1
6
PT0AD1
5
PT0AD1
4
PT0AD1
3
PT0AD1
2
PT0AD1
1
PT0AD1
0
W
0x0279 PT1AD1
R
PT1AD1
7
PT1AD1
6
PT1AD1
5
PT1AD1
4
PT1AD1
3
PT1AD1
2
PT1AD1
1
PT1AD1
0
W
0x027A DDR0AD1
R
DDR0AD1
7
DDR0AD1
6
DDR0AD1
5
DDR0AD1
4
DDR0AD1
3
DDR0AD1
2
DDR0AD1
1
DDR0AD1
0
W
0x027B DDR1AD1
R
DDR1AD1
7
DDR1AD1
6
DDR1AD1
5
DDR1AD1
4
DDR1AD1
3
DDR1AD1
2
DDR1AD1
1
DDR1AD1
0
W
0x027C RDR0AD1
R
RDR0AD1
7
RDR0AD1
6
RDR0AD1
5
RDR0AD1
4
RDR0AD1
3
RDR0AD1
2
RDR0AD1
1
RDR0AD1
0
W
0x027D RDR1AD1
R
RDR1AD1
7
RDR1AD1
6
RDR1AD1
5
RDR1AD1
4
RDR1AD1
3
RDR1AD1
2
RDR1AD1
1
RDR1AD1
0
W
0x027E PER0AD1
R
PER0AD1
7
PER0AD1
6
PER0AD1
5
PER0AD1
4
PER0AD1
3
PER0AD1
2
PER0AD1
1
PER0AD1
0
W
0x027F PER1AD1
R
PER1AD1
7
PER1AD1
6
PER1AD1
5
PER1AD1
4
PER1AD1
3
PER1A1D
2
PER1AD1
1
PER1AD1
0
W
0x0280–0x02BF MSCAN (CAN4) Map
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x0280 CAN4CTL0
R
RXFRM
RXACT
CSWAI
SYNCH
TIME WUPE SLPRQ INITRQ
W
0x0281 CAN4CTL1
R
CANE CLKSRC LOOPB LISTEN BORM WUPM
SLPAK INITAK
W
0x0282 CAN4BTR0
R
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
0x0283 CAN4BTR1
R
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
W
0x0284 CAN4RFLG
R
WUPIF CSCIF
RSTAT1 RSTAT0 TSTAT1 TSTAT0
OVRIF RXF
W
0x0285 CAN4RIER
R
WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
W
0x0286 CAN4TFLG
R00000
TXE2 TXE1 TXE0
W
0x0287 CAN4TIER
R00000
TXEIE2 TXEIE1 TXEIE0
W
0x0288 CAN4TARQ
R00000
ABTRQ2 ABTRQ1 ABTRQ0
W
0x0289 CAN4TAAK
R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0
W
0x028A CAN4TBSEL
R00000
TX2 TX1 TX0
W
0x028B CAN4IDAC
R0 0
IDAM1 IDAM0
0 IDHIT2 IDHIT1 IDHIT0
W
0x028C Reserved
R00000000
W
0x0240–0x027F Port Integration Module (PIM) Map 5 of 6 (continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0