Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 112 (20x20) 16-Bit 50 MHz I/O number 91

HCS12X

Microcontrollers

freescale.com

MC9S12XEP100

Reference Manual

Covers MC9S12XE Family

MC9S12XEP100RMV1

Rev. 1.25

02/2013

Summary of content (1324 pages)

PAGE 1
MC9S12XEP100 Reference Manual Covers MC9S12XE Family HCS12X Microcontrollers MC9S12XEP100RMV1 Rev. 1.25 02/2013 freescale.
PAGE 2
To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verif, refer to: freescale.com This document contains information for the complete S12XE-Family and thus includes a set of separate FTM module sections to cover the whole family. A full list of family members and options is included in the appendices. This document contains information for all constituent modules, with the exception of the S12X CPU.
PAGE 3
Chapter 1 Device Overview MC9S12XE-Family. . . . . . . . . . . . . . . . . . . . . 27 Chapter 2 Port Integration Module (S12XEP100PIMV1) . . . . . . . . . . . . . . 89 Chapter 3 Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . . 187 Chapter 4 Memory Protection Unit (S12XMPUV1) . . . . . . . . . . . . . . . . . 227 Chapter 5 External Bus Interface (S12XEBIV4) . . . . . . . . . . . . . . . . . . . . 241 Chapter 6 Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) . . . . . . . . . . . . 953 Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) . . . . . . . . . . . 1016 Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) . . . . . . . . . . . 1077 Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) . . . . . . . . . 1140 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
Blank Page MC9S12XE-Family Reference Manual Rev. 1.
PAGE 6
Blank Page MC9S12XE-Family Reference Manual Rev. 1.
PAGE 7
Chapter 1 Device Overview MC9S12XE-Family 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
2.2 2.3 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56 2.3.57 2.3.58 2.3.59 2.3.60 2.3.61 2.3.62 2.3.63 2.3.64 2.3.65 2.3.66 2.3.67 2.3.68 2.3.69 2.3.70 2.3.71 2.3.72 2.3.73 2.3.74 2.3.75 2.3.76 2.3.77 2.3.78 2.3.79 2.3.80 2.3.81 2.3.82 2.3.83 2.3.84 2.3.85 2.3.86 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
2.4 2.5 2.3.87 Port R Data Direction Register (DDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.88 Port R Reduced Drive Register (RDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.89 Port R Pull Device Enable Register (PERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 2.3.90 Port R Polarity Select Register (PPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 2.3.
PAGE 11
3.5 3.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 3.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 3.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 12
Chapter 6 Interrupt (S12XINTV2) 6.1 6.2 6.3 6.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 6.1.3 Modes of Operation .
PAGE 13
7.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 7.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Chapter 8 S12X Debug (S12XDBGV3) Module 8.1 8.2 8.3 8.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 8.1.1 Glossary . . . . . . . . . . . . . .
PAGE 14
10.4 10.5 10.6 10.7 10.8 10.9 10.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 10.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 10.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . .
PAGE 15
11.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 Chapter 12 Pierce Oscillator (S12XOSCLCPV2) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 12.1.2 Modes of Operation . . . . . . . . . .
PAGE 16
14.2.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 530 14.2.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 530 14.2.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 530 14.2.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 530 14.2.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . .
PAGE 17
16.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 18
.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 18.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 18.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 19
20.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 20.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 20.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 20
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 22.1.3 Block Diagrams . . . .
PAGE 21
23.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.2.7 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin . . . . . . . . . . . . . . 819 23.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 23.3.1 Module Memory Map . . . .
PAGE 22
25.2 25.3 25.4 25.5 25.6 25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 25.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 External Signal Description . . . . . . . . . . . . . . . . .
PAGE 23
27.2 27.3 27.4 27.5 27.6 27.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 27.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 External Signal Description . . . . . . . . . . . . . . . . . . .
PAGE 24
29.2 29.3 29.4 29.5 29.6 29.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140 29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141 29.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142 External Signal Description . . . . . . . . . . . . . . . . . . .
PAGE 25
A.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 A.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 A.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 A.7 External Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 26
MC9S12XE-Family Reference Manual Rev. 1.
PAGE 27
Chapter 1 Device Overview MC9S12XE-Family 1.1 Introduction The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including new features for enhanced system integrity and greater functionality. These new features include a Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency modulated Phase Locked Loop (IPLL) and an enhanced ATD.
PAGE 28
Chapter 1 Device Overview MC9S12XE-Family • • • • • • • • • • 16-Bit CPU12X — Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) which have been removed — Enhanced indexed addressing — Access to large data segments independent of PPAGE INT (interrupt module) — Eight levels of nested interrupts — Flexible assignment of interrupt sources to each interrupt level.
PAGE 29
Chapter 1 Device Overview MC9S12XE-Family • • • • • • • — No external components required — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) CRG (clock and reset generation) — COP watchdog — Real time interrupt — Clock monitor — Fast wake up from STOP in self clock mode Memory Options — 128K, 256k, 384K, 512K, 768K and 1M byte Flash — 2K, 4K byte emulated EEPROM — 12K, 16K, 24K, 32K, 48K and 64K Byte RAM Flash General Features — 64 data bits plus 8 syndrome ECC
PAGE 30
Chapter 1 Device Overview MC9S12XE-Family • • • • • • • • — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit — Four separate interrupt channels for Rx, Tx, error, and wake-up — Low-pass filter wake-up function — Loop-back for self-test operation ECT (enhanced capture timer) — 8 x 16-bit channels for input capture or output compare — 16-bit free-running counter with 8-bit precision prescaler — 16-bit modulus down counter with 8-bit precision prescaler — Four 8-bit or tw
PAGE 31
Chapter 1 Device Overview MC9S12XE-Family • • • • 1.1.2 Low-power wake-up timer (API) — Available in all modes including Full Stop Mode — Trimmable to +-5% accuracy — Time-out periods range from 0.2ms to ~13s with a 0.
PAGE 32
Chapter 1 Device Overview MC9S12XE-Family 1.1.
PAGE 33
Chapter 1 Device Overview MC9S12XE-Family 1.1.4 Device Memory Map Table 1-1 shows the device register memory map. Table 1-1.
PAGE 34
Chapter 1 Device Overview MC9S12XE-Family Table 1-1.
PAGE 35
Chapter 1 Device Overview MC9S12XE-Family CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS CS3 Unimplemented RAM 0x0000 0x0800 0x0C00 0x1000 RAM 2K REGISTERS 1K EEPROM window EPAGE RAMSIZE RAM_LOW 0x0F_FFFF 1K EEPROM 4K RAM window RPAGE 0x2000 256 K EEEPROM RESOURCES 8K RAM 0x4000 0x13_FFFF CS2 Unpaged 16K FLASH 0x1F_FFFF External Space CS1 0x8000 PPAGE 0x3F_FFFF 0xC000 CS0 16K FLASH window Unimplemented FLASH Unpaged 16K FLASH FLASH_LOW Reset Vector
PAGE 36
Chapter 1 Device Overview MC9S12XE-Family Unimplemented RAM pages are mapped externally in expanded modes. Accessing unimplemented RAM pages in single chip modes causes an illegal address reset if the MPU is not configured to flag an MPU protection error in that range. Accessing unimplemented FLASH pages in single chip modes causes an illegal address reset if the MPU is not configured to flag an MPU protection error in that range.
PAGE 37
Chapter 1 Device Overview MC9S12XE-Family Figure 1-3 shows XGATE local address translation to the global memory map. It indicates also the location of used internal resources in the memory map. Table 1-3. XGATE Resources Internal Resource Size /KByte $Address XGATE RAM 32K XGRAM_LOW = 0x0F_8000 (1) FLASH 30K XGFLASH_HIGH = 0x78_8000 1. This value is calculated by the following formula: (64K -2K- XGRAMSIZE) Table 1-4.
PAGE 38
Chapter 1 Device Overview MC9S12XE-Family Table 1-5. Derivative Dependent Flash Block Mapping (continued) Device 0x70_0000 0x74_0000 9S12XET256 9S12XEA256 — — 0x78_0000 0x7A_0000 0x7C_0000 — — B1S 0x7E_0000 B0(128K) (1) 9S12XEG128 9S12XEA1281 — — B1S (64K) — — B0 (64K) 1. The 9S12XEA devices are special bondouts for access to extra ADC channels in 80QFP. Available in 80QFP only. WARNING: NOT PIN-COMPATIBLE WITH REST OF FAMILY. Block B1 is divided into two 128K blocks.
PAGE 39
Chapter 1 Device Overview MC9S12XE-Family XGATE Local Memory Map Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW 0x0800 RAM 0x0F_FFFF RAMSIZE Registers XGRAMSIZE 0x0000 FLASH RAM 0x78_0800 0xFFFF FLASHSIZE FLASH XGFLASH_HIGH 0x7F_FFFF Figure 1-3. XGATE Global Address Mapping MC9S12XE-Family Reference Manual Rev. 1.
PAGE 40
Chapter 1 Device Overview MC9S12XE-Family 1.1.6 Detailed Register Map The detailed register map is listed in Appendix A. 1.1.7 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID number and Mask Set number. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 41
Chapter 1 Device Overview MC9S12XE-Family The Version ID is a word located in a flash information row at 0x40_00E8. The version ID number indicates a specific version of internal NVM variables used to patch NVM errata. The default is no patch (0xFFFF). Table 1-6.
PAGE 42
Chapter 1 Device Overview MC9S12XE-Family This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device. 1.2.1 Device Pinout The MC9S12XE-Family offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application.
PAGE 43
Chapter 1 Device Overview MC9S12XE-Family 1 2 3 4 5 6 7 8 9 10 11 12 A N.C. N.C. PP7 PM0 PM1 PF5 PF3 PF1 PJ6 PS6 PS5 PS3 B N.C.
PAGE 44
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PP4/KWP4/PWM4/MISO2/TIMIOC4 PP5/KWP5/PWM5/MOSI2/TIMIOC5 PP6/KWP6/PWM6/SS2/TIMIOC6 PP7/KWP7/PWM7/SCK2/TIMIOC7 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXACAN0 TEST PS
PAGE 45
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 Pins shown in BOLD are not available on the 80 QFP package 67 66 65 64 63 62 61 60 59 58 57 MC9S12XE-Family 112LQFP 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VRH VDDA1 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/A
PAGE 46
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PWM4/MISO2/TIMIOC4 PP5/KWP5/PWM5/MOSI2/TIMIOC5 PP7/KWP7/PWM7/SCK2/TIMIOC7 VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 TEST PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA1 VRL Chapter 1 Device Overview MC9S12XE-Family 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MC9S12XE-Family
PAGE 47
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PWM4/MISO2/TIMIOC4 PP5/KWP5/PWM5/MOSI2/TIMIOC5 PP7/KWP7/PWM7/SCK2/TIMIOC7 VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 TEST PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA1 VRL Chapter 1 Device Overview MC9S12XE-Family 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MC9S12XEA256 MC
PAGE 48
Chapter 1 Device Overview MC9S12XE-Family 1.2.2 Pin Assignment Overview Table 1-7 provides a summary of which Ports are available for each package option. Routing of pin functions is summarized in Table 1-8. Table 1-9 provides a pin out summary listing the availability of individual pins for each package option. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 49
Chapter 1 Device Overview MC9S12XE-Family Table 1-10 provides a list of individual pin functionality Table 1-7. Port Availability by Package Option Port 208 MAPBGA 144 LQFP 112 LQFP Standard 80 QFP XEA256(1) 80 QFP Port AD/ADC Channels 32/32 24/24 16/16 8/8 12/12 Port A pins 8 8 8 8 4 Port B pins 8 8 8 8 8 Port C pins 8 8 0 0 0 Port D pins 8 8 0 0 0 Port E pins inc.
PAGE 50
Chapter 1 Device Overview MC9S12XE-Family PF[0] TIM CS3 CS2 CS1 CS0 IIC1 IIC0 SPI2 SPI1 SPI0 SCI7 SCI6 SCI5 SCI4 SCI3 SCI2 SCI1 SCI0 CAN4 CAN3 CAN2 CAN1 CAN0 Table 1-8.
PAGE 51
Chapter 1 Device Overview MC9S12XE-Family PS[1:0] TIM CS3 CS2 CS1 CS0 IIC1 IIC0 SPI2 SPI1 SPI0 SCI7 SCI6 SCI5 SCI4 SCI3 SCI2 SCI1 SCI0 CAN4 CAN3 CAN2 CAN1 CAN0 Table 1-8. Peripheral - Port Routing Options(1) (continued) O PS[3:2] O PS[7:4] O 1. “O” denotes reset condition, “X” denotes a possible rerouting under software control Table 1-9.
PAGE 52
Chapter 1 Device Overview MC9S12XE-Family Table 1-9. Pin-Out Summary (Sheet 2 of 7) LQFP 144 LQFP 112 QFP(1) 80 J4 16 14 10 VSS1 H3 17 15 11 PT4 IOC4 PR4 TIMIOC4 PT5 IOC5 PR5 TIMIOC5 PT6 IOC6 PR6 TIMIOC6 PT7 IOC7 PR7 TIMIOC7 208 MAPBGA H2 J1 18 16 12 J2 J3 19 17 13 K1 K2 20 18 14 K4 Pin 2nd Func. 3rd Func. 4th Func.
PAGE 53
Chapter 1 Device Overview MC9S12XE-Family Table 1-9. Pin-Out Summary (Sheet 3 of 7) 208 MAPBGA LQFP 144 LQFP 112 QFP(1) 80 Pin 2nd Func. T3 41 PC5 DATA13 R5 42 PC6 DATA14 N4 43 PC7 DATA15 PL3 TXD5 PH7 KWH7 PL2 RXD5 PH6 KWH6 PL1 TXD4 PH5 KWH5 PL0 RXD4 PH4 T4 T5 44 32 P5 R6 45 33 N5 T6 46 34 P6 3rd Func. 4th Func.
PAGE 54
Chapter 1 Device Overview MC9S12XE-Family Table 1-9. Pin-Out Summary (Sheet 4 of 7) 208 MAPBGA N11 LQFP 144 LQFP 112 63 51 QFP(1) 80 R12 52 Pin 2nd Func. PH1 KWH1 PL4 RXD6 PH0 KWH0 P11 64 T13 65 PD0 DATA0 R13 66 PD1 DATA1 T14 67 PD2 DATA2 R14 68 PD3 DATA3 VDDX VDDX5 VSSX VSSX5 3rd Func. 4th Func.
PAGE 55
Chapter 1 Device Overview MC9S12XE-Family Table 1-9. Pin-Out Summary (Sheet 5 of 7) LQFP 144 LQFP 112 QFP(1) 80 L15 89 67 51 L16 90 68 208 MAPBGA Pin 2nd Func.
PAGE 56
Chapter 1 Device Overview MC9S12XE-Family Table 1-9.
PAGE 57
Chapter 1 Device Overview MC9S12XE-Family Table 1-9. Pin-Out Summary (Sheet 7 of 7) 208 MAPBGA LQFP 144 LQFP 112 QFP(1) 80 B7 C7 133 101 71 A7 D6 134 102 72 B6 C6 135 103 73 A6 A5 136 104 74 B5 A4 137 105 75 B4 Pin 2nd Func.
PAGE 58
Chapter 1 Device Overview MC9S12XE-Family Table 1-10. Signal Properties Summary (Sheet 1 of 4) Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 Internal Pull Resistor Description CTRL Reset State EXTAL — — — — VDDPLL NA NA NA NA Oscillator pins XTAL — — — — VDDPLL RESET — — — — VDDX TEST — — — — N.A.
PAGE 59
Chapter 1 Device Overview MC9S12XE-Family Table 1-10.
PAGE 60
Chapter 1 Device Overview MC9S12XE-Family Table 1-10.
PAGE 61
Chapter 1 Device Overview MC9S12XE-Family Table 1-10.
PAGE 62
Chapter 1 Device Overview MC9S12XE-Family 1.2.3 Detailed Signal Descriptions NOTE The pin list of the largest package version of each MC9S12XE-Family derivative gives the complete of interface signals that also exist on smaller package options, although some of them are not bonded out. For devices assembled in smaller packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-10 for affected pins.
PAGE 63
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.7 PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data. 1.2.3.8 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins PB[7:1] are general-purpose input or output pins.
PAGE 64
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.13 PE6 / MODB / TAGHI — Port E I/O Pin 6 PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the instruction word being read into the instruction queue.
PAGE 65
Chapter 1 Device Overview MC9S12XE-Family interrupt is level sensitive and active low. As XIRQ is level sensitive, while this pin is low the MCU will not enter STOP mode. 1.2.3.20 PF7 / TXD3 — Port F I/O Pin 7 PF7 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 3 (SCI3). 1.2.3.21 PF6 / RXD3 — Port F I/O Pin 6 PF6 is a general-purpose input or output pin.
PAGE 66
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.28 PH4 / KWH4 / MISO2 / RXD4 — Port H I/O Pin 4 PH4 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). It can be configured as the receive pin RXD of serial communication interface 4 (SCI4). 1.2.3.
PAGE 67
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.35 PJ5 / KWJ5 / SCL1 / CS2 — PORT J I/O Pin 5 PJ5 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as the serial clock pin SCL of the IIC1 module. It can be also configured as chip-select output 2. 1.2.3.36 PJ4 / KWJ4 / SDA1 / CS0 — PORT J I/O Pin 4 PJ4 is a general-purpose input or output pin. It can be configured as a keypad wakeup input.
PAGE 68
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.43 PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0] PK3-PK0 are general-purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information. 1.2.3.44 PL7 / TXD7 — Port L I/O Pin 7 PL7 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 7 (SCI7). 1.2.3.
PAGE 69
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.52 PM7 / TXCAN3 / TXCAN4 / TXD3 — Port M I/O Pin 7 PM7 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM7 can be configured as the transmit pin TXD3 of the serial communication interface 3 (SCI3). 1.2.3.53 PM6 / RXCAN3 / RXCAN4 / RXD3 — Port M I/O Pin 6 PM6 is a general-purpose input or output pin.
PAGE 70
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.60 PP7 / KWP7 / PWM7 / SCK2 / TIMIOC7— Port P I/O Pin 7 PP7 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as pulse width modulator (PWM) channel 7 output, TIM channel 7, or as serial clock pin SCK of the serial peripheral interface 2 (SPI2). 1.2.3.61 PP6 / KWP6 / PWM6 / SS2 / TIMIOC6— Port P I/O Pin 6 PP6 is a general-purpose input or output pin.
PAGE 71
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.67 PP0 / KWP0 / PWM0 / MISO1 / TIMIOC0— Port P I/O Pin 0 PP0 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be configured as pulse width modulator (PWM) channel 0 output, TIM channel 0 or as the master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 1 (SPI1). 1.2.3.
PAGE 72
Chapter 1 Device Overview MC9S12XE-Family 1.2.3.76 PS0 / RXD0 — Port S I/O Pin 0 PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 0 (SCI0). 1.2.3.77 PT[7:6] / IOC[7:6] — Port T I/O Pins [7:6] PT[7:6] are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC[7:6] of the enhanced capture timer (ECT). 1.2.3.
PAGE 73
Chapter 1 Device Overview MC9S12XE-Family 1.2.4.4 VDDF — NVM Power Pin Power is supplied to the MCU NVM through VDDF . The voltage supply of nominally 2.8V is derived from the internal voltage regulator. No static external loading of these pins is permitted. 1.2.4.5 VDDA2, VDDA1, VSSA2, VSSA1 — Power Supply Pins for ATD and Voltage Regulator These are the power supply and ground input pins for the analog-to-digital converters and the voltage regulator. Internally the VDDA pins are connected together.
PAGE 74
Chapter 1 Device Overview MC9S12XE-Family Table 1-11. Power and Ground Connection Summary (continued) Mnemonic Nominal Voltage VDDPLL 1.8 V VSSPLL 0V Description Provides operating voltage and ground for the phased-locked loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 75
Chapter 1 Device Overview MC9S12XE-Family 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-9 shows the clock connections from the CRG to all modules. Consult the CRG specification for details on clock generation. SCI0 . . SCI 7 CAN0 . . CAN4 SPI0 . .
PAGE 76
Chapter 1 Device Overview MC9S12XE-Family The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock. The oscillator clock is used as a time base to derive the program and erase times for the NVM’s. The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock. This allows the user to select its clock based on the required jitter performance.
PAGE 77
Chapter 1 Device Overview MC9S12XE-Family The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MMCCTL1 register on the rising edge of RESET. Table 1-12.
PAGE 78
Chapter 1 Device Overview MC9S12XE-Family 1.4.1.5 Emulation of Single-Chip Mode Developers use this mode for emulation systems in which the user’s target application is normal singlechip mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface. 1.4.1.6 Special Test Mode This is for Freescale internal use only. 1.4.
PAGE 79
Chapter 1 Device Overview MC9S12XE-Family 1.4.2.4 XGATE Fake Activity Mode This mode is entered if the CPU executes the STOP instruction when the XGATE is not executing a thread and the XGFACT bit in the XGMCTL register is set. The oscillator remains active and any enabled peripherals continue to function. 1.4.2.5 Wait Mode This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off.
PAGE 80
Chapter 1 Device Overview MC9S12XE-Family MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as defined in the Memory Protection Unit (MPU) description. 1.4.4.2 User State This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes register while in Supervisor state.
PAGE 81
Chapter 1 Device Overview MC9S12XE-Family Table 1-14.
PAGE 82
Chapter 1 Device Overview MC9S12XE-Family Table 1-14.
PAGE 83
Chapter 1 Device Overview MC9S12XE-Family Table 1-14.
PAGE 84
Chapter 1 Device Overview MC9S12XE-Family Table 1-14.
PAGE 85
Chapter 1 Device Overview MC9S12XE-Family is loaded with valid data from the D-Flash EEE partition. Completion of this phase is indicated by the CCIF flag in the FTM FSTAT register becoming set. If the CPU accesses any EEE RAM location before the CCIF flag is set, the CPU is stalled until the FTM reset sequence is complete and the EEE RAM data is valid. Once the CCIF flag is set, indicating the end of this phase, the EEE RAM can be accessed without impacting the CPU and FTM commands can be executed. 1.6.
PAGE 86
Chapter 1 Device Overview MC9S12XE-Family 1.7 1.7.1 ADC0 Configuration External Trigger Input Connection The ADC module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger allows the user to synchronize ADC conversion to external trigger events. Table 1-17 shows the connection of the external trigger inputs. Table 1-17.
PAGE 87
Chapter 1 Device Overview MC9S12XE-Family 1.9 MPU Configuration The MPU has the option of a third bus master (CPU + XGATE + other) which is not present on this device family but may be on other parts. 1.10 VREG Configuration The VREGEN connection of the voltage regulator is tied internally to VDDR such that the voltage regulator is always enabled with VDDR connected to a positive supply voltage. The device must be configured with the internal voltage regulator enabled.
PAGE 88
Chapter 1 Device Overview MC9S12XE-Family 1.13 Oscillator Configuration The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. For this device XCLKS is mapped to PE7. The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing.
PAGE 89
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-1. Revision History Revision Number Revision Date V01.17 02 Apr 2008 V01.18 25 Nov 2008 V01.19 18 Dec 2009 2.1 2.1.1 Sections Affected Description of Changes • Corrected reduced drive strength to 1/5 • Separated PE1,0 bit descriptions from other PE GPIO 2.3.19/120 2.4.3.
PAGE 90
Chapter 2 Port Integration Module (S12XEPIMV1) • Port F associated with IIC, SCI and chip select outputs Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and select pull-up or pull-down devices. NOTE This document assumes the availability of all features (208-pin package option). Some functions are not available on lower pin count package options. Refer to the pin-out summary in the SOC Guide. 2.1.
PAGE 91
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-2 shows all the pins and their functions that are controlled by the Port Integration Module. Refer to the SOC Guide for the availability of the individual pins in the different package options. NOTE If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Table 2-2.
PAGE 92
Chapter 2 Port Integration Module (S12XEPIMV1) Port Pin Name Pin Function & Priority(1) I/O E PE[7] XCLKS 2 I External clock selection input during RESET ECLKX2 I Free-running clock output at Core Clock rate (ECLK x 2) GPIO PE[6] MODB GPIO PE[4] PE[2] Instruction tagging low pin Configurable for reduced input threshold I MODA input during RESET O Read enable signal TAGLO I Instruction tagging low pin Configurable for reduced input threshold GPIO I/O General-purpose I/O ECLK O F
PAGE 93
Chapter 2 Port Integration Module (S12XEPIMV1) Port Pin Name Pin Function & Priority(1) T PT[7] IOC[7] I/O Enhanced Capture Timer Channels 7 input/output GPIO I/O General-purpose I/O IOC[5] I/O Enhanced Capture Timer Channel 5 input/output PT[5] VREG_API GPIO PT[4:0] IOC[4:0] GPIO S PS7 SS0 I/O O Description VREG Autonomous Periodical Interrupt output I/O Enhanced Capture Timer Channels 4 - 0 input/output I/O General-purpose I/O I/O Serial Peripheral Interface 0 slave select output in
PAGE 94
Chapter 2 Port Integration Module (S12XEPIMV1) Port Pin Name Pin Function & Priority(1) I/O M PM7 TXCAN3 O MSCAN3 transmit pin (TXCAN4) O MSCAN4 transmit pin TXD3 O Serial Communication Interface 3 transmit pin GPIO I/O General-purpose I/O PM6 RXCAN3 I MSCAN3 receive pin (RXCAN4) I MSCAN4 receive pin RXD3 I Serial Communication Interface 3 receive pin GPIO PM5 O MSCAN2 transmit pin (TXCAN0) O MSCAN0 transmit pin (TXCAN4) O MSCAN4 transmit pin GPIO PM4 I MSCAN2 receive
PAGE 95
Chapter 2 Port Integration Module (S12XEPIMV1) Port Pin Name Pin Function & Priority(1) P PP7 PWM7 I/O Pulse Width Modulator input/output channel 7 SCK2 I/O Serial Peripheral Interface 2 serial clock pin (TIMIOC7) GPIO/KWP7 PP6 PWM6 SS2 (TIMIOC6) GPIO/KWP6 PP5 I/O Timer Channel 6 input/output I/O General-purpose I/O with interrupt Pulse Width Modulator output channel 5 I/O Timer Channel 5 input/output I/O General-purpose I/O with interrupt MISO2 I/O Serial Peripheral Interface 2 master in/sl
PAGE 96
Chapter 2 Port Integration Module (S12XEPIMV1) Pin Function after Reset Port Pin Name Pin Function & Priority(1) H PH7 (SS2) I/O Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode TXD5 O GPIO/KWH7 PH6 (SCK2) RXD5 GPIO/KWH6 PH5 (MOSI2) TXD4 GPIO/KWH5 PH4 (MISO2) RXD4 GPIO/KWH4 PH3 (SS1) TXD7 GPIO/KWH3 PH2 (SCK1) RXD7 GPIO/KWH2 PH1 (MOSI1) TXD6 GPIO/KWH1 PH0 (MISO1) TXD6 GPIO/KWH0 I/O Description GPIO Serial Communication Interface
PAGE 97
Chapter 2 Port Integration Module (S12XEPIMV1) Port Pin Name Pin Function & Priority(1) I/O J PJ7 TXCAN4 O MSCAN4 transmit pin SCL0 O Inter Integrated Circuit 0 serial clock line (TXCAN0) O MSCAN0 transmit pin GPIO/KWJ7 PJ6 RXCAN4 SDA0 (RXCAN0) GPIO/KWJ6 PJ5 I/O General-purpose I/O with interrupt O Chip select 2 I/O General-purpose I/O with interrupt I/O Inter Integrated Circuit 1 serial data line O Chip select 0 GPIO/KWJ3 I/O General-purpose I/O with interrupt CS1 TXD2 GPIO/KWJ1 P
PAGE 98
Chapter 2 Port Integration Module (S12XEPIMV1) Port Pin Name Pin Function & Priority(1) I/O L PL7 (TXD7) O GPIO PL6 (RXD7) PL5 (TXD6) GPIO GPIO PL4 (RXD6) PL3 (TXD5) GPIO GPIO PL2 (RXD5) PL1 (TXD4) GPIO GPIO PL0 (RXD4) PF7 (TXD3) GPIO F GPIO PF6 (RXD3) PF5 (SCL0) GPIO GPIO Description Serial Communication Interface 7 transmit pin GPIO I/O General-purpose I/O I Serial Communication Interface 7 receive pin I/O General-purpose I/O O Serial Communication Interface 6 transmit
PAGE 99
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.
PAGE 100
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name Bit 7 6 5 0x000E– R 0x001B W Non-PIM Address Range 0x001C R ECLKCTL W 0x001D R Reserved W 0x001E IRQCR W 0x001F R Reserved R 0x0033 DDRK 0x0241 PTIT 2 1 Bit 0 NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 IRQE IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R W R W Non-PIM Address Range PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 0x0034– R
PAGE 101
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0x0246 R Reserved W 0 0 0 0 0 0 0 0 0x0247 R Reserved W 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
PAGE 102
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name 0x0253 RDRM W 0x0254 PERM W 0x0255 PPSM R R R W 0x0256 WOMM W 0x0257 MODRR W 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP R R R W R R W R W R W W 0x025E PIEP W R R R W 0x0260 PTH W 0x0261 PTIH W 0x0262 DDRH 6 5 4 3 2 1 Bit 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 WOMM7 W
PAGE 103
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name 0x0263 RDRH 0x0264 PERH 0x0265 PPSH 0x0266 PIEH R W R W R W R W 0x0267 PIFH W 0x0268 PTJ W 0x0269 PTIJ R R R W 0x026B RDRJ W 0x026D PPSJ 0x026E PIEJ 0x026F PIFJ 0x0270 PT0AD0 0x0271 PT1AD0 6 5 4 3 2 1 Bit 0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
PAGE 104
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0272 R DDR0AD0 W DDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00 0x0273 R DDR1AD0 W DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0x0274 R RDR0AD0 W RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00 0x0275 R RDR1AD0 W RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0x0276 R PER0AD0 W PER0AD07 PER0AD06 PER0AD05 PER0
PAGE 105
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name 0x0368 PTR W 0x0369 PTIR W 0x036A DDRR R R R W 0x036B RDRR W 0x036C PERR W 0x036D PPSR R R R W 0x036E R Reserved W 0x036F PTRRR 0x0370 PTL R W R W 0x0371 PTIL W 0x0372 DDRL W 0x0373 RDRL R R R W 0x0374 PERL W 0x0375 PPSL W 0x0376 WOML 0x0377 PTLRR R R R W R W Bit 7 6 5 4 3 2 1 Bit 0 PTR7 PTR6 PTR5 PTR4 PTR3 PTR2 PTR1 PTR0 PTIR7 PTIR6 PTIR5 PTIR4 PTIR3 PTIR2 PTIR1 PTIR0 DDRR7 DDRR6 DDRR5
PAGE 106
Chapter 2 Port Integration Module (S12XEPIMV1) Register Name 0x0378 PTF 0x0379 PTIF 0x037A DDRF 0x037B RDRF R W R 6 5 4 3 2 1 Bit 0 PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0 DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 RDRF7 RDRF6 RDRF5 RDRF4 RDRF3 RDRF2 RDRF1 RDRF0 PERF7 PERF6 PERF5 PERF4 PERF3 PERF2 PERF1 PERF0 PPSF7 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0 0 0 0 0 0 0 0 0 0 0 PTFRR5 PTFR
PAGE 107
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-3.
PAGE 108
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.3 Port A Data Register (PORTA) Access: User read/write(1) Address 0x0000 (PRR) 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ADDR15 mux IVD15 ADDR14 mux IVD14 ADDR13 mux IVD13 ADDR12 mux IVD12 ADDR11 mux IVD11 ADDR10 mux IVD10 ADDR9 mux IVD9 ADDR8 mux IVD8 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-1. Port A Data Register (PORTA) 1. Read: Anytime.
PAGE 109
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-5. PORTB Register Field Descriptions Field Description 7-0 PB Port B general purpose input/output data—Data Register Port B pins 7 through 0 are associated with address outputs ADDR[7:0] respectively in expanded modes. In emulation modes the address is multiplexed with IVD[7:0]. In normal expanded mode pin 0 is related to the UDS input. When not used with the alternative function, these pins can be used as general purpose I/O.
PAGE 110
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-7. DDRB Register Field Descriptions Field Description 7-0 DDRB Port B Data Direction— This register controls the data direction of pins 7 through 0. The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output.
PAGE 111
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.8 Port D Data Register (PORTD) Access: User read/write(1) Address 0x0005 (PRR) 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-6. Port D Data Register (PORTD) 1. Read: Anytime.
PAGE 112
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-10. DDRC Register Field Descriptions Field Description 7-0 DDRC Port C Data Direction— This register controls the data direction of pins 7 through 0. The external bus function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output.
PAGE 113
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.11 Port E Data Register (PORTE) Access: User read/write(1) Address 0x0008 (PRR) 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 XCLKS or ECLKX2 MODB or TAGHI MODA or RE or TAGLO ECLK EROMCTL or LSTRB or LDS RW or WE IRQ XIRQ 0 0 0 0 0 0 —(2) —2 R W Altern. Function Reset = Unimplemented or Reserved Figure 2-9. Port E Data Register (PORTE) 1. Read: Anytime.
PAGE 114
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.12 Port E Data Direction Register (DDRE) Access: User read/write(1) Address 0x0009 (PRR) 7 6 5 4 3 2 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-10. Port E Data Direction Register (DDRE) 1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value.
PAGE 115
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-14. PUCR Register Field Descriptions Field Description 7 PUPKE Pull-up Port K Enable—Enable pull-up devices on all Port K input pins This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are enabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled.
PAGE 116
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.14 S12X_EBI ports Reduced Drive Register (RDRIV) Access: User read/write(1) Address 0x000D (PRR) 7 R 6 5 0 0 RDPK 4 3 2 1 0 RDPE RDPD RDPC RDPB RDPA 0 0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 2-12. S12X_EBI ports Reduced Drive Register (RDRIV) 1. Read: Anytime.
PAGE 117
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-15. RDRIV Register Field Descriptions (continued) Field Description 1 RDPB Port B reduced drive—Select reduced drive for outputs This bit configures the drive strength of all output pins as either full or reduced independent of the function used on the pins. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled.
PAGE 118
Chapter 2 Port Integration Module (S12XEPIMV1) The ECLKCTL register is used to control the availability of the free-running clocks and the free-running clock divider. Table 2-16. ECLKCTL Register Field Descriptions Field Description 7 NECLK No ECLK—Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always active in emulation modes and if enabled in all other operating modes.
PAGE 119
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.17 IRQ Control Register (IRQCR) Access: User read/write(1) Address 0x001E 7 6 IRQE IRQEN 0 1 R 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-15. IRQ Control Register (IRQCR) 1. Read: See individual bit descriptions below. Write: See individual bit descriptions below. Table 2-17.
PAGE 120
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.19 Port K Data Register (PORTK) Access: User read/write(1) Address 0x0032 (PRR) 7 6 5 4 3 2 1 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 ROMCTL or EWAIT ADDR22 mux ACC2 ADDR21 mux ACC1 ADDR20 mux ACC0 ADDR19 mux IQSTAT3 ADDR18 mux IQSTAT2 ADDR17 mux IQSTAT1 ADDR16 mux IQSTAT0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-17. Port K Data Register (PORTK) 1. Read: Anytime.
PAGE 121
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-19. DDRK Register Field Descriptions Field Description 7-0 DDRK Port K Data Direction— This register controls the data direction of pins 7 through 0. The external bus function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output.
PAGE 122
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.22 Port T Input Register (PTIT) Access: User read(1) Address 0x0241 R 7 6 5 4 3 2 1 0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 u u u u u u u u W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-20. Port T Input Register (PTIT) 1. Read: Anytime. Write:Never, writes to this register have no effect. Table 2-21.
PAGE 123
Chapter 2 Port Integration Module (S12XEPIMV1) NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register. 2.3.24 Port T Reduced Drive Register (RDRT) Access: User read/write(1) Address 0x0243 7 6 5 4 3 2 1 0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 2-22. Port T Reduced Drive Register (RDRT) 1. Read: Anytime. Write: Anytime.
PAGE 124
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.26 Port T Polarity Select Register (PPST) Access: User read/write(1) Address 0x0245 7 6 5 4 3 2 1 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 R W Reset Figure 2-24. Port T Polarity Select Register (PPST) 1. Read: Anytime. Write: Anytime. Table 2-25. PPST Register Field Descriptions Field 7-0 PPST 2.3.
PAGE 125
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.29 Port S Data Register (PTS) Access: User read/write(1) Address 0x0248 7 6 5 4 3 2 1 0 PTS7 PTST6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-27. Port S Data Register (PTS) 1. Read: Anytime. Write: Anytime. Table 2-26.
PAGE 126
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-26. PTS Register Field Descriptions (continued) Field Description 1 PTS Port S general purpose input/output data—Data Register Port S pin 3 is associated with the TXD signal of the SCI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
PAGE 127
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-28. DDRS Register Field Descriptions Field Description 7-0 DDRS Port S data direction— This register controls the data direction of pins 7 through 0.This register configures each Port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
PAGE 128
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.33 Port S Pull Device Enable Register (PERS) Access: User read/write(1) Address 0x024C 7 6 5 4 3 2 1 0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 1 1 1 1 1 1 1 1 R W Reset Figure 2-31. Port S Pull Device Enable Register (PERS) 1. Read: Anytime. Write: Anytime. Table 2-30.
PAGE 129
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.35 Port S Wired-Or Mode Register (WOMS) Access: User read/write(1) Address 0x024E 7 6 5 4 3 2 1 0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 R W Reset Figure 2-33. Port S Wired-Or Mode Register (WOMS) 1. Read: Anytime. Write: Anytime. Table 2-32.
PAGE 130
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.37 Port M Data Register (PTM) Access: User read/write(1) Address 0x0250 7 6 5 4 3 2 1 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 TXCAN3 RXCAN3 TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 — — (TXCAN0) (RXCAN0) (TXCAN0) (RXCAN0) — — (TXCAN4) (RXCAN4) (TXCAN4) (RXCAN4) — — — — — — (SCK0) (MOSI0) (SS0) (MISO0) — — TXD3 RXD3 — — — — — — 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-35.
PAGE 131
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-33. PTM Register Field Descriptions (continued) Field Description 4 PTM Port M general purpose input/output data—Data Register Port M pin 4 is associated with the RXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with MOSI signals of SPI0. The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose I/O function if the CAN2 module is enabled.
PAGE 132
Chapter 2 Port Integration Module (S12XEPIMV1) 1. Read: Anytime. Write:Never, writes to this register have no effect. Table 2-34. PTIM Register Field Descriptions Field Description 7-0 PTIM Port M input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. 2.3.
PAGE 133
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-35. DDRM Register Field Descriptions (continued) Field Description 4 DDRM Port M data direction— This register controls the data direction of pin 4. The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change.
PAGE 134
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.40 Port M Reduced Drive Register (RDRM) Access: User read/write(1) Address 0x0253 7 6 5 4 3 2 1 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 0 0 0 0 0 0 0 0 R W Reset Figure 2-38. Port M Reduced Drive Register (RDRM) 1. Read: Anytime. Write: Anytime. Table 2-36.
PAGE 135
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.42 Port M Polarity Select Register (PPSM) Access: User read/write(1) Address 0x0255 7 6 5 4 3 2 1 0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 0 0 0 0 R W Reset Figure 2-40. Port M Polarity Select Register (PPSM) 1. Read: Anytime. Write: Anytime. Table 2-38.
PAGE 136
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.44 Module Routing Register (MODRR) Access: User read/write(1) Address 0x0257 7 R 6 5 4 3 2 1 0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 2-42. Module Routing Register (MODRR) 1. Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Table 2-40.
PAGE 137
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.45 Port P Data Register (PTP) Access: User read/write(1) Address 0x0258 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SCK2 SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-43. Port P Data Register (PTP) 1. Read: Anytime. Write: Anytime. Table 2-41.
PAGE 138
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-41. PTP Register Field Descriptions (continued) Field Description 3 PTP Port P general purpose input/output data—Data Register Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1. The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
PAGE 139
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-42. PTIP Register Field Descriptions Field Description 7-0 PTIP Port P input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. 2.3.
PAGE 140
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.48 Port P Reduced Drive Register (RDRP) Access: User read/write(1) Address 0x025B 7 6 5 4 3 2 1 0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-46. Port P Reduced Drive Register (RDRP) 1. Read: Anytime. Write: Anytime. Table 2-44. RDRP Register Field Descriptions Field 7-0 RDRP 2.3.
PAGE 141
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.50 Port P Polarity Select Register (PPSP) Access: User read/write(1) Address 0x025D 7 6 5 4 3 2 1 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-48. Port P Polarity Select Register (PPSP) 1. Read: Anytime. Write: Anytime. Table 2-46.
PAGE 142
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.52 Port P Interrupt Flag Register (PIFP) Access: User read/write(1) Address 0x025F 7 6 5 4 3 2 1 0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 R W Reset Figure 2-50. Port P Interrupt Flag Register (PIFP) 1. Read: Anytime. Write: Anytime. Table 2-48. PPSP Register Field Descriptions Field Description 7-0 PIFP Port P interrupt flag— Each flag is set by an active edge on the associated input pin.
PAGE 143
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-49. PTH Register Field Descriptions Field Description 7 PTH Port H general purpose input/output data—Data Register Port H pin 7 is associated with the TXD signal of the SCI5 module and the SS signal of the routed SPI2. The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2 module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
PAGE 144
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-49. PTH Register Field Descriptions (continued) Field Description 1 PTH Port H general purpose input/output data—Data Register Port H pin 1 is associated with the TXD signal of the SCI6 module and the MOSI signal of the routed SPI1. The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1 module is enabled.
PAGE 145
Chapter 2 Port Integration Module (S12XEPIMV1) 1. Read: Anytime. Write: Anytime. Table 2-51. DDRH Register Field Descriptions Field Description 7 DDRH Port H data direction— This register controls the data direction of pin 7. The enabled SCI5 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2 this pin will be forced to be input or output. In those cases the data direction bits will not change.
PAGE 146
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-51. DDRH Register Field Descriptions (continued) Field Description 1 DDRH Port H data direction— This register controls the data direction of pin 1. The enabled SCI6 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1 this pin will be forced to be input or output. In those cases the data direction bits will not change.
PAGE 147
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.57 Port H Pull Device Enable Register (PERH) Access: User read/write(1) Address 0x0264 7 6 5 4 3 2 1 0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 0 0 0 0 0 0 0 0 R W Reset Figure 2-55. Port H Pull Device Enable Register (PERH) 1. Read: Anytime. Write: Anytime. Table 2-53.
PAGE 148
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.59 Port H Interrupt Enable Register (PIEH) Read: Anytime. Access: User read/write(1) Address 0x0266 7 6 5 4 3 2 1 0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 0 0 0 0 0 0 0 0 R W Reset Figure 2-57. Port H Interrupt Enable Register (PIEH) 1. Read: Anytime. Write: Anytime. Table 2-55. PPSP Register Field Descriptions Field 7-0 PIEH 2.3.
PAGE 149
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.61 Port J Data Register (PTJ) Access: User read/write(1) Address 0x0268 7 6 5 4 3 2 1 0 PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 TXCAN4 RXCAN4 — — — — TXD2 RXD2 SCL0 SDA0 SCL1 SDA1 — — — — (TXCAN0) (RXCAN0) CS2 CS0 — CS1 — CS3 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-59. Port J Data Register (PTJ) 1. Read: Anytime. Write: Anytime. Table 2-57.
PAGE 150
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-57. PTJ Register Field Descriptions (continued) Field Description 1 PTJ Port J general purpose input/output data—Data Register This pin is associated with the TXD signal of SCI2. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
PAGE 151
Chapter 2 Port Integration Module (S12XEPIMV1) 1. Read: Anytime. Write: Anytime. Table 2-59. DDRJ Register Field Descriptions Field Description 7 DDRJ Port J data direction— This register controls the data direction of pin 7. The enabled CAN4 or routed CAN0 forces the I/O state to be an output. The enabled IIC0 module forces this pin to be a open drain output. In those cases the data direction bits will not change.
PAGE 152
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-59. DDRJ Register Field Descriptions (continued) Field Description 1 DDRJ Port J data direction— This register controls the data direction of pin 1. The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
PAGE 153
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.65 Port J Pull Device Enable Register (PERJ) Access: User read/write(1) Address 0x026C 7 6 5 4 3 2 1 0 PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 1 1 1 1 1 1 1 1 R W Reset Figure 2-63. Port J Pull Device Enable Register (PERJ) 1. Read: Anytime. Write: Anytime. Table 2-61.
PAGE 154
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.67 Port J Interrupt Enable Register (PIEJ) Read: Anytime. Access: User read/write(1) Address 0x026E 7 6 5 4 3 2 1 0 PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 0 0 0 0 0 0 0 0 R W Reset Figure 2-65. Port J Interrupt Enable Register (PIEJ) 1. Read: Anytime. Write: Anytime. Table 2-63. PPSP Register Field Descriptions Field 7-0 PIEJ 2.3.
PAGE 155
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.69 Port AD0 Data Register 0 (PT0AD0) Access: User read/write(1) Address 0x0270 7 6 5 4 3 2 1 0 PT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-67. Port AD0 Data Register 0 (PT0AD0) 1. Read: Anytime. Write: Anytime. Table 2-65.
PAGE 156
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.71 Port AD0 Data Direction Register 0 (DDR0AD0) Access: User read/write(1) Address 0x0272 7 6 5 4 3 2 1 0 DDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00 0 0 0 0 0 0 0 0 R W Reset Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0) 1. Read: Anytime. Write: Anytime. Table 2-67.
PAGE 157
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-68. DDR1AD0 Register Field Descriptions Field Description 7-0 Port AD0 data direction— DDR1AD0 This register controls the data direction of pins 7 through 0. 1 Associated pin is configured as output. 0 Associated pin is configured as input. NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT0AD0 registers, when changing the DDR1AD0 register.
PAGE 158
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.74 Port AD0 Reduced Drive Register 1 (RDR1AD0) Access: User read/write(1) Address 0x0275 7 6 5 4 3 2 1 0 RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 2-72. Port AD0 Reduced Drive Register 1 (RDR1AD0) 1. Read: Anytime. Write: Anytime. Table 2-70.
PAGE 159
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.76 Port AD0 Pull Up Enable Register 1 (PER1AD0) Access: User read/write(1) Address 0x0277 7 6 5 4 3 2 1 0 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 2-74. Port AD0 Pull Up Enable Register 1 (PER1AD0) 1. Read: Anytime. Write: Anytime. Table 2-72.
PAGE 160
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.78 Port AD1 Data Register 1 (PT1AD1) Access: User read/write(1) Address 0x0279 7 6 5 4 3 2 1 0 PT1AD17 PT1AD16 PT1AD15 PT1AD14 PT1AD13 PT1AD12 PT1AD11 PT1AD10 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-76. Port AD1 Data Register 1 (PT1AD1) 1. Read: Anytime. Write: Anytime. Table 2-74.
PAGE 161
Chapter 2 Port Integration Module (S12XEPIMV1) NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT0AD1 registers, when changing the DDR0AD1 register. NOTE To use the digital input function on Port AD1 the ATD Digital Input Enable Register (ATD1DIEN1) has to be set to logic level “1”. 2.3.
PAGE 162
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.81 Port AD1 Reduced Drive Register 0 (RDR0AD1) Access: User read/write(1) Address 0x027C 7 6 5 4 3 2 1 0 RDR0AD17 RDR0AD16 RDR0AD15 RDR0AD14 RDR0AD13 RDR0AD12 RDR0AD11 RDR0AD10 0 0 0 0 0 0 0 0 R W Reset Figure 2-79. Port AD1 Reduced Drive Register 0 (RDR0AD1) 1. Read: Anytime. Write: Anytime. Table 2-77.
PAGE 163
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.83 Port AD1 Pull Up Enable Register 0 (PER0AD1) Access: User read/write(1) Address 0x027E 7 6 5 4 3 2 1 0 PER0AD17 PER0AD16 PER0AD15 PER0AD14 PER0AD13 PER0AD12 PER0AD11 PER0AD10 0 0 0 0 0 0 0 0 R W Reset Figure 2-81. Port AD1 Pull Device Up Register 0 (PER0AD1) 1. Read: Anytime. Write: Anytime. Table 2-79.
PAGE 164
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.85 Port R Data Register (PTR) Access: User read/write(1) Address 0x0368 7 6 5 4 3 2 1 0 PTR7 PTR6 PTR5 PTR4 PTR3 PTR2 PTR1 PTR0 TIMIOC7 TIMIOC6 TIMIOC5 TIMIOC4 TIMIOC3 TIMIOC2 TIMIOC1 TIMIOC0 0 0 0 0 0 0 0 0 R W Altern. Function Reset Figure 2-83. Port R Data Register (PTR) 1. Read: Anytime. Write: Anytime. Table 2-81.
PAGE 165
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.87 Port R Data Direction Register (DDRR) Access: User read/write(1) Address 0x036A 7 6 5 4 3 2 1 0 DDRR7 DDRR6 DDRR5 DDRR4 DDRR3 DDRR2 DDRR1 DDRR0 0 0 0 0 0 0 0 0 R W Reset Figure 2-85. Port R Data Direction Register (DDRR) 1. Read: Anytime. Write: Anytime. Table 2-83. DDRR Register Field Descriptions Field Description 7-0 DDRR Port R data direction— This register controls the data direction of pins 7 through 0.
PAGE 166
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-84. RDRR Register Field Descriptions Field 7-0 RDRR 2.3.89 Description Port R reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the function used on the pins. If a pin is used as input this bit has no effect. 1 Reduced drive selected (approx. 1/5 of the full drive strength). 0 Full drive strength enabled.
PAGE 167
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-86. PPSR Register Field Descriptions Field 7-0 PPSR 2.3.91 Description Port R pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PAGE 168
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-87. PTR Routing Register Field Descriptions (continued) Field Description 5 PTRRR Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC5 is available on PP5 0 TIMIOC5 is available on PR5 4 PTRRR Port R routing— This register configures the re-routing of the associated TIM channel.
PAGE 169
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-88. PTL Register Field Descriptions Field Description 7 PTL Port L general purpose input/output data—Data Register Port L pin 7 is associated with the TXD signal of the SCI7 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
PAGE 170
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.94 Port L Input Register (PTIL) Access: User read(1) Address 0x0371 R 7 6 5 4 3 2 1 0 PTIL7 PTIL6 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0 u u u u u u u u W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-92. Port L Input Register (PTIL) 1. Read: Anytime. Write:Never, writes to this register have no effect. Table 2-89.
PAGE 171
Chapter 2 Port Integration Module (S12XEPIMV1) NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTL or PTIL registers, when changing the DDRL register. 2.3.96 Port L Reduced Drive Register (RDRL) Access: User read/write(1) Address 0x0373 7 6 5 4 3 2 1 0 RDRL7 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0 0 0 0 0 0 0 0 0 R W Reset Figure 2-94. Port L Reduced Drive Register (RDRL) 1. Read: Anytime. Write: Anytime.
PAGE 172
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.98 Port L Polarity Select Register (PPSL) Access: User read/write(1) Address 0x0375 7 6 5 4 3 2 1 0 PPSL7 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0 0 0 0 0 0 0 0 0 R W Reset Figure 2-96. Port L Polarity Select Register (PPSL) 1. Read: Anytime. Write: Anytime. Table 2-93. PPSL Register Field Descriptions Field 7-0 PPSL 2.3.
PAGE 173
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.100 Port L Routing Register (PTLRR) Access: User read/write(1) Address 0x0377 7 6 5 4 PTLRR7 PTLRR6 PTLRR5 PTLRR4 0 0 0 0 R 3 2 1 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-98. Port L Routing Register (PTLRR) 1. Read: Anytime. Write: Anytime. This register configures the re-routing of SCI7, SCI6, SCI5, and SCI4 on alternative ports. Table 2-95.
PAGE 174
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-96. PTF Register Field Descriptions Field Description 7 PTF Port F general purpose input/output data—Data Register Port F pin 7 is associated with the TXD signal of the SCI3 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
PAGE 175
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.102 Port F Input Register (PTIF) Access: User read(1) Address 0x0379 R 7 6 5 4 3 2 1 0 PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0 u u u u u u u u W Reset = Unimplemented or Reserved u = Unaffected by reset Figure 2-100. Port F Input Register (PTIF) 1. Read: Anytime. Write:Never, writes to this register have no effect. Table 2-97.
PAGE 176
Chapter 2 Port Integration Module (S12XEPIMV1) NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTF or PTIF registers, when changing the DDRF register. 2.3.104 Port F Reduced Drive Register (RDRF) Access: User read/write(1) Address 0x037B 7 6 5 4 3 2 1 0 RDRF7 RDRF6 RDRF5 RDRF4 RDRF3 RDRF2 RDRF1 RDRF0 0 0 0 0 0 0 0 0 R W Reset Figure 2-102. Port F Reduced Drive Register (RDRF) 1. Read: Anytime. Write: Anytime.
PAGE 177
Chapter 2 Port Integration Module (S12XEPIMV1) 2.3.106 Port F Polarity Select Register (PPSF) Access: User read/write(1) Address 0x037D 7 6 5 4 3 2 1 0 PPSF7 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0 0 0 0 0 0 0 0 0 R W Reset Figure 2-104. Port F Polarity Select Register (PPSF) 1. Read: Anytime. Write: Anytime. Table 2-101.
PAGE 178
Chapter 2 Port Integration Module (S12XEPIMV1) This register configures the re-routing of SCI3, IIC0, CS[3:0] on alternative ports. Table 2-102. Port F Routing Summary Module PTFRR 5 SCI3 IIC0 4 3 2 Related Pins 1 0 TXD RXD 0 x x x x x PM7 PM6 1 x x x x x PF7 PF6 SCL SDA x 0 x x x x PJ7 PJ6 x 1 x x x x PF5 PF4 CS CS3 CS2 CS1 CS0 2.4 2.4.
PAGE 179
Chapter 2 Port Integration Module (S12XEPIMV1) Table 2-103.
PAGE 180
Chapter 2 Port Integration Module (S12XEPIMV1) PTI 0 1 PT 0 PIN 1 DDR 0 1 data out Module output enable module enable Figure 2-107. Illustration of I/O pin functionality 2.4.2.4 Reduced drive register (RDRx) If the pin is used as an output this register allows the configuration of the drive strength. 2.4.2.5 Pull device enable register (PERx) This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-or output. 2.4.2.
PAGE 181
Chapter 2 Port Integration Module (S12XEPIMV1) 2.4.2.9 Interrupt flag register (PIFx) If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. 2.4.2.10 Module routing register (MODRR, PTRRR, PTLRR, PTFRR) This register supports the re-routing of the CAN0, CAN4, SPI2-0, SCI7-3, IIC0, TIM and CS[3:0] pins to alternative ports. This allows a software re-configuration of the pinouts of the different package options with respect to above peripherals. 2.4.
PAGE 182
Chapter 2 Port Integration Module (S12XEPIMV1) Port E pin PE[6] can be used for either general-purpose I/O, as TAGHI input or as MODB input during reset. Port E pin PE[5] can be used for either general-purpose I/O, as TAGLO input, RE output or as MODA input during reset. Port E pin PE[4] can be used for either general-purpose I/O or as the free-running clock ECLK output running at the Bus Clock rate or at the programmed divided clock rate. The clock output is always enabled in emulation modes.
PAGE 183
Chapter 2 Port Integration Module (S12XEPIMV1) The SPI0 pins can be re-routed. 2.4.3.8 Port M This port is associated with the SCI3 CAN4-0 and SPI0. Port M pins PM[7:6] can be used for either general purpose I/O, or with the CAN3 subsystem. Port M pins PM[5:4] can be used for either general purpose I/O, or with the CAN2 subsystem. Port M pins PM[3:2] can be used for either general purpose I/O, or with the CAN1 subsystem.
PAGE 184
Chapter 2 Port Integration Module (S12XEPIMV1) Port J pin PJ[3] can be used for general purpose I/O. Port J pin PJ[2] can be used for either general purpose I/O or as chip select output. Port J pin PJ[1] can be used for either general purpose I/O, or with the SCI2 subsystem. Port J pin PJ[0] can be used for either general purpose I/O, or with the SCI2 subsystem or as chip select output. 2.4.3.12 Port AD0 This port is associated with the ATD0.
PAGE 185
Chapter 2 Port Integration Module (S12XEPIMV1) 2.4.4 Pin interrupts Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set.
PAGE 186
Chapter 2 Port Integration Module (S12XEPIMV1) tpulse Figure 2-109. Pulse Illustration A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by an RC-oscillator in the Port Integration Module.
PAGE 187
Chapter 3 Memory Mapping Control (S12XMMCV4) Table 3-1. Revision History Revision Number Revision Date V04.04 26 Oct 2005 V04.05 26 Jul 2006 V04.06 15 Nov 2006 3.1 Sections Affected Description of Changes - Reorganization of MEMCTL0 register bits. 3.4.2.4/3-212 - Updated XGATE Memory Map - Adding AUTOSAR Compliance concerning illegal CPU accesses Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform.
PAGE 188
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.1.1 Terminology Table 3-2.
PAGE 189
Chapter 3 Memory Mapping Control (S12XMMCV4) • • • • • • • • Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 3-1 ) Resolution of target bus access collision MCU operation mode control MCU security control Separate memory map schemes for each master CPU, BDM and XGATE ROM control bits to enable the on-chip FLASH or ROM selection Port replacement registers access control Generation of system reset when CPU accesses an unimplemented address (i.e.
PAGE 190
Chapter 3 Memory Mapping Control (S12XMMCV4) • Expanded modes Address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus. Access to internal resources will not cause activity on the external bus. Emulation modes External bus is active to emulate, via an external tool, the normal expanded or the normal single chip mode.} • 3.1.5 Block Diagram Figure 3-11 shows a block diagram of the MMC.
PAGE 191
Chapter 3 Memory Mapping Control (S12XMMCV4) Table 3-3. External Input Signals Associated with the MMC Signal I/O Description Availability MODC I Mode input Latched after RESET (active low) MODB I Mode input Latched after RESET (active low) MODA I Mode input Latched after RESET (active low) EROMCTL I EROM control input Latched after RESET (active low) ROMCTL I ROM control input Latched after RESET (active low) Table 3-4.
PAGE 192
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.3 3.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
PAGE 193
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.3.2 Register Descriptions 3.3.2.1 MMC Control Register (MMCCTL0) Address: 0x000A PRR R W Reset 7 6 5 4 3 2 1 0 CS3E1 CS3E0 CS2E1 CS2E0 CS1E1 CS1E0 CS0E1 CS0E0 0 0 0 0 0 0 0 ROMON1 1. ROMON is bit[0] of the register MMCTL1 (see Figure 3-10) = Unimplemented or Reserved Figure 3-3. MMC Control Register (MMCCTL0) Read: Anytime. In emulation modes read operations will return the data from the external bus.
PAGE 194
Chapter 3 Memory Mapping Control (S12XMMCV4) Table 3-6. MMCCTL0 Field Descriptions Field Description 7–6 CS3E[1:0] Chip Select 3 Enables — These bits enable the external chip select CS3 output which is asserted during accesses to specific external addresses. The associated global address range is shown in Table 3-7 and Figure 3-17. Chip select 3 is only active if enabled in Normal Expanded mode, Emulation Expanded mode. The function disabled in all other operating modes.
PAGE 195
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.3.2.2 Mode Register (MODE) Address: 0x000B PRR 7 R W Reset 6 5 MODC MODB MODA MODC1 MODB1 MODA1 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 3-3). = Unimplemented or Reserved Figure 3-4. Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all other modes the data are read from this register. Write: Only if a transition is allowed (see Figure 3-5).
PAGE 196
Chapter 3 Memory Mapping Control (S12XMMCV4) RESET 010 Special Test (ST) 010 1 1 10 0 10 Normal Expanded (NX) 101 Emulation Single-Chip (ES) 001 Emulation Expanded (EX) 011 101 10 1 011 RESET 0 10 RESET RESET 000 001 101 101 010 110 111 Normal Single-Chip (NS) 100 1 00 01 RESET 100 1 01 1 00 Special Single-Chip (SS) 000 000 RESET Transition done by external pins (MODC, MODB, MODA) RESET Transition done by write access to the MODE register 110 111 Illegal (MODC, MODB, MO
PAGE 197
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.3.2.3 Global Page Index Register (GPAGE) Address: 0x0010 7 R 0 W Reset 0 6 5 4 3 2 1 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 3-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used to construct a 23 bit address in the global map format.
PAGE 198
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.3.2.4 Direct Page Register (DIRECT) Address: 0x0011 R W 7 6 5 4 3 2 1 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 Reset Figure 3-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. Table 3-10.
PAGE 199
Chapter 3 Memory Mapping Control (S12XMMCV4) ;many cases assemblers are “direct page aware” and can ;automatically select direct mode. 3.3.2.5 MMC Control Register (MMCCTL1) Address: 0x0013 PRR 7 R W 6 0 TGMRAMON Reset 0 0 5 4 3 2 1 0 EEEIFRON PGMIFRON RAMHM EROMON ROMHM ROMON 0 0 0 EROMCTL 0 ROMCTL = Unimplemented or Reserved Figure 3-10. MMC Control Register (MMCCTL1) Read: Anytime. In emulation modes read operations will return the data from the external bus.
PAGE 200
Chapter 3 Memory Mapping Control (S12XMMCV4) Table 3-11. MMCCTL1 Field Descriptions (continued) Field 2 EROMON Description Enables emulated Flash or ROM memory in the memory map Write: Never This bit is used in some modes to define the placement of the Emulated Flash or ROM (Refer to Table 3-12) 0 Disables the emulated Flash or ROM in the memory map. 1 Enables the emulated Flash or ROM in the memory map.
PAGE 201
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.3.2.6 Program Page Index Register (PPAGE) Address: 0x0015 R W Reset 7 6 5 4 3 2 1 0 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 1 1 1 1 1 1 1 0 Figure 3-11. Program Page Index Register (PPAGE) Read: Anytime Write: Anytime These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local (CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12).
PAGE 202
Chapter 3 Memory Mapping Control (S12XMMCV4) The fixed 16K page from 0x4000–0x7FFF (when ROMHM = 0) is the page number 0xFD. The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and 0xFFFF out of reset. The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF. 3.3.2.7 RAM Page Index Register (RPAGE) Address: 0x0016 R W Reset 7 6 5 4 3 2 1 0 RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 1 1 1 1 1 1 0 1 Figure 3-13.
PAGE 203
Chapter 3 Memory Mapping Control (S12XMMCV4) Table 3-14. RPAGE Field Descriptions Field Description 7–0 RP[7:0] RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to be accessed in the RAM Page Window. The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and 0x3FFF out of reset. The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
PAGE 204
Chapter 3 Memory Mapping Control (S12XMMCV4) Global Address [22:0] 0 0 1 0 0 Bit17 Bit16 Bit10 Bit9 Bit0 Address [9:0] EPAGE Register [7:0] Address: CPU Local Address or BDM Local Address Figure 3-16. EPAGE Address Mapping Table 3-15. EPAGE Field Descriptions Field 7–0 EP[7:0] Description EEPROM Page Index Bits 7–0 — These page index bits are used to select which of the 256 EEPROM array pages is to be accessed in the EEPROM Page Window.
PAGE 205
Chapter 3 Memory Mapping Control (S12XMMCV4) • • • • Emulation single-chip mode Tool vendors use this mode for emulation systems in which the user’s target application is normal single-chip mode. Code is executed from external or internal memory depending on the set-up of the EROMON bit (see Section 3.3.2.5, “MMC Control Register (MMCCTL1)). The external bus is active in both cases to allow observation of internal operations (internal visibility).
PAGE 206
Chapter 3 Memory Mapping Control (S12XMMCV4) CPU and BDM Local Memory Map Global Memory Map 0x00_0000 2K REGISTERS 0x00_0800 2K RAM RAM 253*4K paged 0x0800 0x0C00 0x1000 0x0F_E000 2K REGISTERS 8K RAM 1K EEPROM window EPAGE 0x10_0000 1K EEPROM EEPROM 255*1K paged RPAGE 4K RAM window 0x2000 8K RAM 0x4000 0x13_FC00 256 Kilobytes 0x0000 1M minus 2 Kilobytes 0x00_1000 1K EEPROM 0x14_0000 2.
PAGE 207
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. The page value for the program page window is stored in the PPAGE register.
PAGE 208
Chapter 3 Memory Mapping Control (S12XMMCV4) Expansion of the BDM Local Address Map PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. 3.4.2.
PAGE 209
Chapter 3 Memory Mapping Control (S12XMMCV4) BDM HARDWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 BDMGPR Register [6:0] Bit0 BDM Local Address BDM FIRMWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 BDMGPR Register [6:0] Bit0 CPU Local Address Figure 3-18. BDMGPR Address Mapping 3.4.2.3 Implemented Memory Map The global memory spaces reserved for the internal resources (RAM, EEE, and FLASH) are not determined by the MMC module.
PAGE 210
Chapter 3 Memory Mapping Control (S12XMMCV4) In emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip resources (unimplemented areas) result in accesses to the external bus. CPU accesses to global addresses which are occupied by external memory space result in an illegal access reset (system reset) in case of no MPU error. BDM accesses to the external space are performed but the data will be undefined.
PAGE 211
Chapter 3 Memory Mapping Control (S12XMMCV4) CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS CS3 Unimplemented RAM 0x0000 0x0800 0x0C00 0x1000 RAM 2K REGISTERS 1K EEPROM window EPAGE RAMSIZE RAM_LOW 0x0F_FFFF 1K EEPROM 4K RAM window RPAGE 0x2000 256 K EEEPROM 8K RAM 0x4000 0x13_FFFF CS2 Unpaged 16K FLASH 0x1F_FFFF External Space CS1 0x8000 PPAGE 0x3F_FFFF 0xC000 CS0 16K FLASH window Unimplemented FLASH Unpaged 16K FLASH Reset Vectors FLASH_LOW FLASH
PAGE 212
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.4.2.4 3.4.2.4.1 XGATE Memory Map Scheme Expansion of the XGATE Local Address Map The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the BDM module (see Table 3-18). XGATE can access the FLASH in single chip modes, even when the MCU is secured. In expanded modes, XGATE can not access the FLASH when MCU is secured.
PAGE 213
Chapter 3 Memory Mapping Control (S12XMMCV4) XGATE Local Memory Map Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW 0x0800 RAM 0x0F_FFFF RAMSIZE Registers XGRAMSIZE 0x0000 FLASH 0x7FFF XGRAMSIZE Unimplemented area RAM 0x78_0800 0xFFFF FLASHSIZE FLASH 0x78_7FFF 0x7F_FFFF Figure 3-20. XGATE Global Address Mapping MC9S12XE-Family Reference Manual Rev. 1.
PAGE 214
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.4.2.5 Memory Configuration Two bits in the MMCCTL1 register (ROMHM, RAMHM) configure the mapping of the local address (0x4000-0x7FFF) in the global memory map. ROMHM, RAMHM are write once in normal and emulation modes and anytime in special modes. Three areas are identified (See Figure 3-21): • Program FLASH (0x7F_4000-0x7F_7FFF) when ROMHM = 0. • External Space (0x14_4000-0x14_7FFF) when ROMHM = 1 and RAMHM = 0.
PAGE 215
Chapter 3 Memory Mapping Control (S12XMMCV4) CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_0800 2K REGISTERS 2K RAM RAM 251*4K paged 0x0F_A000 8K RAM 0x0800 0x0C00 0x1000 2K REGISTERS 1K EEPROM window 16K RAM 0x10_0000 1K EEPROM EEPROM 255*1K paged 4K RAM window 0x2000 8K RAM 0x4000 0x13_FC00 256 Kilobytes 0x0000 ROMHM RAMHM 0x0F_C000 1 1 1M minus 2 Kilobytes 0x00_1000 1K EEPROM 1 16K External 0 0x8000 External Space 2.
PAGE 216
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.4.2.5.1 System XSRAM System XSRAM has two ways to be accessed by the CPU. One is by the programming of RPAGE and the fixed XSRAM areas configured by the values of ROMHM, RAMHM, or by the usage of the global instruction and the usage of GPAGE. Figure 3-22 shows the memory map for the implemented XSRAM. The size of the implemented XSRAM is done by the device definition and denoted by RAMSIZE.
PAGE 217
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.4.3 Chip Access Restrictions CPU and XGATE accesses are watched in the memory protection unit (See MPU Block Guide). In case of access violation, the suspect master is acknowledged with an indication of an error; the victim target will not be accessed. Other violations MPU is not handling are listed below. 3.4.3.
PAGE 218
Chapter 3 Memory Mapping Control (S12XMMCV4) BDM CPU DBG XGATE XGATE FLEXRAY S12X1 S12X0 S12X2 MMC “Crossbar Switch” EBI XBUS0 XBUS1 BLKX XBUS3 FTM FLASH EEE XRAM BDM resources XSRAM XBUS2 IPBI Figure 3-23. MMC Block Diagram 3.4.4.1 Master Bus Prioritization regarding access conflicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time.
PAGE 219
Chapter 3 Memory Mapping Control (S12XMMCV4) called can be located anywhere in the local address space or in any Flash or ROM page visible through the program page window. The CALL instruction calculates and stacks a return address, stacks the current PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value controls which of the 256 possible pages is visible through the 16 Kbyte program page window in the 64 Kbyte local CPU memory map.
PAGE 220
Chapter 3 Memory Mapping Control (S12XMMCV4) in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution. 3.5.2 Port Replacement Registers (PRRs) Registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full emulation of single chip mode operation. These registers are called port replacement registers (PRRs) (see Table 1-25).
PAGE 221
Chapter 3 Memory Mapping Control (S12XMMCV4) Table 3-21. PRR Listing 3.5.
PAGE 222
Chapter 3 Memory Mapping Control (S12XMMCV4) No External Bus MCU Flash Figure 3-24. ROM in Single Chip Modes 3.5.3.2 ROM Control in Emulation Single-Chip Mode In emulation single-chip mode the external bus is connected to the emulator. If the EROMON bit is set, the internal FLASH provides the data and the emulator can observe all internal CPU actions on the external bus. If the EROMON bit is cleared, the emulator provides the data (generator) and traces the all CPU actions (see Figure 3-25).
PAGE 223
Chapter 3 Memory Mapping Control (S12XMMCV4) MCU Application Memory Flash ROMON = 1 MCU Application Memory ROMON = 0 Figure 3-26. ROM in Normal Expanded Mode MC9S12XE-Family Reference Manual Rev. 1.
PAGE 224
Chapter 3 Memory Mapping Control (S12XMMCV4) 3.5.3.4 ROM Control in Emulation Expanded Mode In emulation expanded mode the external bus will be connected to the emulator and to the application. If the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU actions (see Figure 3-27).
PAGE 225
Chapter 3 Memory Mapping Control (S12XMMCV4) Observer MCU Emulator Application Memory Figure 3-28. ROMON = 0 in Emulation Expanded Mode 3.5.3.5 ROM Control in Special Test Mode In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal FLASH provides the data, otherwise the application memory provides the data (see Figure 3-29). Application MCU Memory ROMON = 0 Application MCU Flash Memory ROMON = 1 Figure 3-29.
PAGE 226
Chapter 3 Memory Mapping Control (S12XMMCV4) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 227
Chapter 4 Memory Protection Unit (S12XMPUV1) Table 4-1. Revision History Revision Number Revision Date Sections Affected V01.04 14 Sep 2005 4.3.1.1/4-231 4.4.1/4-237 - Added note to only use the CPU to clear the AE flag. - Added disclaimer to avoid changing descriptors while they are in use because of other bus-masters doing accesses. V01.05 14 Mar 2006 4.3.1.1/4-231 4.4/4-237 - Clarified that interrupt generation is independent of AEF bit state.
PAGE 228
Chapter 4 Memory Protection Unit (S12XMPUV1) access is allowed or represents an access violation. If an access violation caused by the S12X CPU is detected, the MPU module raises an access violation interrupt. If the MPU module detects an access violation caused by a bus master other than the S12X CPU, it flags an access error condition to the respective master.
PAGE 229
Chapter 4 Memory Protection Unit (S12XMPUV1) • • 4.1.
PAGE 230
Chapter 4 Memory Protection Unit (S12XMPUV1) 4.3.1 Register Descriptions This section describes in address order all the MPU module registers and their individual bits.
PAGE 231
Chapter 4 Memory Protection Unit (S12XMPUV1) 4.3.1.1 MPU Flag Register (MPUFLG) Address: Module Base + 0x0000 7 R W Reset AEF 0 6 5 4 3 2 1 0 WPF NEXF 0 0 0 0 SVSF 0 0 0 0 0 0 0 Figure 4-3. MPU Flag Register (MPUFLG) Read: Anytime Write: Write of 1 clears flag, write of 0 ignored Table 4-3. MPUFLG Field Descriptions Field Description 7 AEF Access Error Flag — This bit is the CPU access error interrupt flag. It is set if a CPU access violation has occurred.
PAGE 232
Chapter 4 Memory Protection Unit (S12XMPUV1) 4.3.1.2 MPU Address Status Register 0 (MPUASTAT0) Address: Module Base + 0x0001 7 R 6 5 4 0 3 2 1 0 0 0 0 ADDR[22:16] W Reset 0 0 0 0 0 Figure 4-4. MPU Address Status Register 0 (MPUASTAT0) Read: Anytime Write: Never Table 4-4. MPUASTAT0 Field Descriptions Field Description 6–0 Access violation address bits — The ADDR[22:16] bits contain bits [22:16] of the global address which ADDR[22:16] caused the current access violation interrupt.
PAGE 233
Chapter 4 Memory Protection Unit (S12XMPUV1) 4.3.1.4 MPU Address Status Register 2 (MPUASTAT2) Address: Module Base + 0x0003 7 6 5 4 R 3 2 1 0 0 0 0 0 ADDR[7:0] W Reset 0 0 0 0 Figure 4-6. MPU Address Status Register (MPUASTAT2) Read: Anytime Write: Never Table 4-6. MPUASTAT2 Field Descriptions Field Description 7–0 ADDR[7:0] Access violation address bits — The ADDR[7:0] bits contain bits [7:0] of the global address which caused the current access violation interrupt.
PAGE 234
Chapter 4 Memory Protection Unit (S12XMPUV1) 4.3.1.6 MPU Descriptor Register 0 (MPUDESC0) Address: Module Base + 0x0006 R W 7 6 5 4 3 MSTR0 MSTR1 MSTR2 MSTR3 2 1 0 LOW_ADDR[22:19] 0 Reset 1(1) 11 1(2) 11 1. initialized as set for descriptor 0 only, cleared for all others 2. initialized as set for descriptor 0 only, if MSTR3 is implemented on the device 0 0 0 Figure 4-8. MPU Descriptor Register 0 (MPUDESC0) Read: Anytime Write: Anytime Table 4-8.
PAGE 235
Chapter 4 Memory Protection Unit (S12XMPUV1) Table 4-9. MPUDESC1 Field Descriptions Field Description Memory range lower boundary address bits — The LOW_ADDR[18:11] bits represent bits [18:11] of the 7–0 LOW_ADDR[ global memory address that is used as the lower boundary for the described memory range. 18:11] 4.3.1.8 MPU Descriptor Register 2 (MPUDESC2) Address: Module Base + 0x0008 7 6 5 R 3 2 1 0 0 0 0 LOW_ADDR[10:3] W Reset 4 0 0 0 0 0 Figure 4-10.
PAGE 236
Chapter 4 Memory Protection Unit (S12XMPUV1) Field Description 6 NEX No-Execute bit — The NEX bit prevents the described memory range from being used as code memory. If this bit is set every Op-code fetch in this memory range causes an access violation. 3–0 Memory range upper boundary address bits — The HIGH_ADDR[22:19] bits represent bits [22:19] of the HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range. 22:19] 4.3.1.
PAGE 237
Chapter 4 Memory Protection Unit (S12XMPUV1) 4.4 Functional Description The MPU module provides memory protection for accesses coming from multiple masters in the system. This is done by monitoring bus traffic of each master and compare this with the configuration information from a set of eight programmable descriptors located in the MPU module. If the MPU module detects an access violation caused by the S12X CPU, it will assert the CPU access violation interrupt signal.
PAGE 238
Chapter 4 Memory Protection Unit (S12XMPUV1) NOTE Configuring the lower boundary address of a descriptor to be higher than the upper boundary address of a descriptor causes this descriptor to be ignored by the comparator block. This effectively disables the descriptor. NOTE Avoid changing descriptors while they are in active use to validate accesses from bus-masters. This can be done by temporarily disabling the affected master during the update (XGATE, Master 3, switch S12X CPU states).
PAGE 239
Chapter 4 Memory Protection Unit (S12XMPUV1) ranges with the NEX bit set adjacent to memory used for program code. The best way to do this would be to leave some fill-bytes between the memory ranges in this case, i.e. do not set the upper memory boundary to the address of the last op-code but to a following address which is at least two words (four bytes) away. 4.4.2 Interrupts This section describes all interrupts originated by the MPU module. 4.4.2.
PAGE 240
Chapter 4 Memory Protection Unit (S12XMPUV1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 241
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-1. Revision History Revision Number Revision Date V04.01 12 Sep 2005 - Added CSx stretch description. V04.02 23 May 2006 - Internal updates V04.03 24 Jul 2006 5.1 Sections Affected Description of Changes - Removed term IVIS Introduction This document describes the functionality of the XEBI block controlling the external bus interface. The XEBI controls the functionality of a non-multiplexed external bus (a.k.a.
PAGE 242
Chapter 5 External Bus Interface (S12XEBIV4) 5.1.
PAGE 243
Chapter 5 External Bus Interface (S12XEBIV4) Refer to the S12X_MMC section for a detailed description of the MCU operating modes. 5.1.4 Block Diagram Figure 5-1 is a block diagram of the XEBI with all related I/O signals. ADDR[22:0] DATA[15:0] IVD[15:0] LSTRB RW EWAIT XEBI UDS LDS RE WE ACC[2:0] IQSTAT[3:0] CS[3:0] Figure 5-1. XEBI Block Diagram 5.2 External Signal Description The user is advised to refer to the SoC section for port configuration and location of external bus signals.
PAGE 244
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-2.
PAGE 245
Chapter 5 External Bus Interface (S12XEBIV4) 5.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XEBI. 5.3.1 Module Memory Map The registers associated with the XEBI block are shown in Figure 5-2. Register Name 0x0E EBICTL0 0x0F EBICTL1 Bit 7 R W 6 4 3 2 1 Bit 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 EXSTR11 EXSTR10 EXSTR02 EXSTR01 EXSTR00 0 ITHRS R 5 0 EXSTR12 W 0 = Unimplemented or Reserved Figure 5-2.
PAGE 246
Chapter 5 External Bus Interface (S12XEBIV4) This register controls input pin threshold level and determines the external address and data bus sizes in normal expanded mode. If not in use with the external bus interface, the related pins can be used for alternative functions. External bus is available as programmed in normal expanded mode and always full-sized in emulation modes and special test mode; function not available in single-chip modes. Table 5-3.
PAGE 247
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-5. External Address Bus Size 5.3.2.2 ASIZ[4:0] Available External Address Lines 00011 ADDR[2:1], UDS : : 10110 ADDR[21:1], UDS 10111 : 11111 ADDR[22:1], UDS External Bus Interface Control Register 1 (EBICTL1) Module Base +0x000F (PRR) 7 R 6 0 W Reset 5 4 EXSTR12 EXSTR11 EXSTR10 1 1 1 0 3 0 2 1 0 EXSTR02 EXSTR01 EXSTR00 1 1 1 0 = Unimplemented or Reserved Figure 5-4.
PAGE 248
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-7. EBICTL1 Field Descriptions Field Description 6–4 External Access Stretch Option 1 Bits 2, 1, 0 — This three bit field determines the amount of additional clock EXSTR1[2:0] stretch cycles on every access to the external address space as shown in Table 5-8.
PAGE 249
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-9.
PAGE 250
Chapter 5 External Bus Interface (S12XEBIV4) 5.4.2.1 Access Source Signals (ACC) The access source can be determined from the external bus control signals ACC[2:0] as shown in Table 510. Table 5-10. Determining Access Source from Control Signals ACC[2:0] Access Description 000 Repetition of previous access cycle 001 CPU access 010 BDM external access 011 XGATE PRR access 100 No access(1) 101 CPU access error 110, 111 Reserved 1.
PAGE 251
Chapter 5 External Bus Interface (S12XEBIV4) The resulting timing pattern of the external bus signals is outlined in the following tables for read, write and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus cycles. Non-shaded bold entries denote all values related to Access #0.
PAGE 252
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-14. Read Access (n–1 Cycles) DATA[15:0] (external read) ... ? z z z z z ... data 0 z ... RW ... 1 1 1 1 1 1 ... 1 1 ... 5.4.2.4.2 Write Access Timing Table 5-15. Write Access (1 Cycle) Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ... ADDR[15:0] / IVD[15:0] Access #0 Access #1 Access #2 1 2 3 high low high low iqstat -1 addr 0 addr 1 iqstat 0 ? ...
PAGE 253
Chapter 5 External Bus Interface (S12XEBIV4) Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle) (continued) ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ... ADDR[15:0] / IVD[15:0] ... DATA[15:0] (internal read) ... high low addr 0 iqstat -1 high low addr 1 iqstat 0 acc 0 ... acc 2 ... addr 2 iqstat 1 ... x ... z ... (write) data 1 z ... 0 1 ... ivd 0 z z DATA[15:0] (external read) ... ? z data 0 RW ... 1 1 0 5.4.
PAGE 254
Chapter 5 External Bus Interface (S12XEBIV4) Read data are not captured in emulation expanded mode until the specified setup time before the falling edge of ECLK. In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is not supported.
PAGE 255
Chapter 5 External Bus Interface (S12XEBIV4) internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 5-20. Table 5-20.
PAGE 256
Chapter 5 External Bus Interface (S12XEBIV4) 5.4.6 Low-Power Options The XEBI does not support any user-controlled options for reducing power consumption. 5.4.6.1 Run Mode The XEBI does not support any options for reducing power in run mode. Power consumption is reduced in single-chip modes due to the absence of the external bus interface.
PAGE 257
Chapter 5 External Bus Interface (S12XEBIV4) 5.5.1.1 Example 1a: External Wait Feature Disabled The first example of bus timing of an external read and write access with the external wait feature disabled is shown in • Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’ The associated supply voltage dependent timing are numbers given in • Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAIT disabled)’ • Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 3.
PAGE 258
Chapter 5 External Bus Interface (S12XEBIV4) state operation (stretching) of the external bus access is done in emulation modes when accessing internal memory or emulation memory addresses. In both modes observation of the internal operation is supported through the external bus (internal visibility). 5.5.2.1 Example 2a: Emulation Single-Chip Mode This mode is used for emulation systems in which the target application is operating in normal single-chip mode.
PAGE 259
Chapter 5 External Bus Interface (S12XEBIV4) • • ECLKX2 rising edges have the same timing as ECLK edges. The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing for an external non-PRR access with 1 cycle of stretch as shown in example 2b. 5.5.2.2 Example 2b: Emulation Expanded Mode This mode is used for emulation systems in which the target application is operating in normal expanded mode.
PAGE 260
Chapter 5 External Bus Interface (S12XEBIV4) • Table ‘Example 2b: Emulation Expanded Mode Timing VDD5 = 5.0 V (EWAIT disabled)’ (this also includes examples for alternative settings of 2 and 3 additional stretch cycles) Timing considerations: • If no stretch cycle is added, the timing is the same as in Emulation Single-Chip Mode. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 261
Chapter 6 Interrupt (S12XINTV2) Table 6-1. Revision History Revision Number Revision Date Sections Affected V02.00 01 Jul 2005 6.1.2/6-262 V02.04 11 Jan 2007 6.3.2.2/6-267 6.3.2.4/6-268 V02.05 20 Mar 2007 6.4.6/6-274 V02.07 13 Dec 2011 6.5.3.1/6-276 6.1 Description of Changes Initial V2 release, added new features: - XGATE threads can be interrupted. - SYS instruction vector. - Access violation interrupt vectors. - Added Notes for devices without XGATE module.
PAGE 262
Chapter 6 Interrupt (S12XINTV2) 6.1.1 Glossary The following terms and abbreviations are used in the document. Table 6-2. Terminology Term CCR Condition Code Register (in the S12X CPU) DMA Direct Memory Access INT Interrupt IPL Interrupt Processing Level ISR Interrupt Service Routine MCU XGATE IRQ XIRQ 6.1.
PAGE 263
Chapter 6 Interrupt (S12XINTV2) 6.1.3 • • • • Modes of Operation Run mode This is the basic mode of operation. Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 6.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode In stop mode, the XINT module is frozen.
PAGE 264
Chapter 6 Interrupt (S12XINTV2) 6.1.4 Block Diagram Figure 6-1 shows a block diagram of the XINT module.
PAGE 265
Chapter 6 Interrupt (S12XINTV2) 6.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XINT module. 6.3.1 Module Memory Map Table 6-3 gives an overview over all XINT module registers. Table 6-3.
PAGE 266
Chapter 6 Interrupt (S12XINTV2) 6.3.2 Register Descriptions This section describes in address order all the XINT module registers and their individual bits.
PAGE 267
Chapter 6 Interrupt (S12XINTV2) 6.3.2.1 Interrupt Vector Base Register (IVBR) Address: 0x0121 7 6 5 R 3 2 1 0 1 1 1 IVB_ADDR[7:0] W Reset 4 1 1 1 1 1 Figure 6-3. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Table 6-4. IVBR Field Descriptions Field Description 7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e.
PAGE 268
Chapter 6 Interrupt (S12XINTV2) Table 6-6. XGATE Interrupt Priority Levels Priority low high 6.3.2.
PAGE 269
Chapter 6 Interrupt (S12XINTV2) Address: 0x0128 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 6-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x0129 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 6-7.
PAGE 270
Chapter 6 Interrupt (S12XINTV2) Address: 0x012C 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 6-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 1. Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x012D 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 1(1) = Unimplemented or Reserved Figure 6-11.
PAGE 271
Chapter 6 Interrupt (S12XINTV2) Table 6-8. INT_CFDATA0–7 Field Descriptions Field Description 7 RQST XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module.
PAGE 272
Chapter 6 Interrupt (S12XINTV2) 6.4.1 S12X Exception Requests The CPU handles both reset requests and interrupt requests. The XINT module contains registers to configure the priority level of each I bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the priority of a pending interrupt request. 6.4.
PAGE 273
Chapter 6 Interrupt (S12XINTV2) 6.4.3 XGATE Requests If the XGATE module is implemented on the device, the XINT module is also used to process all exception requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed in the subsections below. 6.4.3.1 XGATE Request Prioritization An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the associated configuration register is set to 1 (please refer to Section 6.3.2.
PAGE 274
Chapter 6 Interrupt (S12XINTV2) NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)). 6.4.5 Reset Exception Requests The XINT module supports three system reset exception request types (for details please refer to the Clock and Reset Generator module (CRG)): 1.
PAGE 275
Chapter 6 Interrupt (S12XINTV2) 6.5 6.5.1 Initialization/Application Information Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module).
PAGE 276
Chapter 6 Interrupt (S12XINTV2) 0 Stacked IPL IPL in CCR 0 0 4 0 0 0 4 7 4 3 1 0 7 6 RTI L7 5 4 RTI Processing Levels 3 L3 (Pending) 2 L4 RTI 1 L1 (Pending) 0 RTI Reset Figure 6-14. Interrupt Processing Example 6.5.3 6.5.3.1 Wake Up from Stop or Wait Mode CPU Wake Up from Stop or Wait Mode Only I bit maskable interrupt requests which are configured to be handled by the CPU are capable of waking the MCU from wait mode.
PAGE 277
Chapter 6 Interrupt (S12XINTV2) 6.5.3.2 XGATE Wake Up from Stop or Wait Mode Interrupt request channels which are configured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 278
Chapter 6 Interrupt (S12XINTV2) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 279
Chapter 7 Background Debug Module (S12XBDMV2) Table 7-1. Revision History Revision Number Revision Date V02.00 07 Mar 2006 - First version of S12XBDMV2 V02.01 14 May 2008 - Introduced standardized Revision History Table V02.02 12 Sep 2012 - Minor formatting corrections 7.1 Sections Affected Description of Changes Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12X core platform.
PAGE 280
Chapter 7 Background Debug Module (S12XBDMV2) • • • • • • • • • • • • • Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single chip mode Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 14 firmware commands execute from the standard BDM firmware lookup table Software control of BDM operation during wait mode Software selectable clocks Global page access function
PAGE 281
Chapter 7 Background Debug Module (S12XBDMV2) 7.1.2.3 Low-Power Modes The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM firmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available.
PAGE 282
Chapter 7 Background Debug Module (S12XBDMV2) 7.3 Memory Map and Register Definition 7.3.1 Module Memory Map Table 7-2 shows the BDM memory map when BDM is active. Table 7-2. BDM Memory Map 7.3.2 Global Address Module Size (Bytes) 0x7FFF00–0x7FFF0B BDM registers 12 0x7FFF0C–0x7FFF0E BDM firmware ROM 3 0x7FFF0F Family ID (part of BDM firmware ROM) 1 0x7FFF10–0x7FFFFF BDM firmware ROM 240 Register Descriptions A summary of the registers associated with the BDM is shown in Figure 7-2.
PAGE 283
Chapter 7 Background Debug Module (S12XBDMV2) Global Address Register Name 0x7FFF07 Bit 7 6 5 4 3 0 0 0 0 0 BGAE BGP6 BGP5 BGP4 0 0 0 0 0 0 0 BDMCCRH R 2 1 Bit 0 CCR10 CCR9 CCR8 BGP3 BGP2 BGP1 BGP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0x7FFF08 BDMGPR R W 0x7FFF09 Reserved R W 0x7FFF0A Reserved R W 0x7FFF0B Reserved R W = Unimplemented, Reserved = Indeterminate X = Implemented (do not alter) = Always read zero 0 Figure 7-2.
PAGE 284
Chapter 7 Background Debug Module (S12XBDMV2) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, but subject to the following: — ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single chip and emulation modes). — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode.
PAGE 285
Chapter 7 Background Debug Module (S12XBDMV2) Table 7-3. BDMSTS Field Descriptions (continued) Field Description 2 CLKSW Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send.
PAGE 286
Chapter 7 Background Debug Module (S12XBDMV2) 7.3.2.2 BDM CCR LOW Holding Register (BDMCCRL) Register Global Address 0x7FFF06 7 6 5 4 3 2 1 0 CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 Special Single-Chip Mode 1 1 0 0 1 0 0 0 All Other Modes 0 0 0 0 0 0 0 0 R W Reset Figure 7-4.
PAGE 287
Chapter 7 Background Debug Module (S12XBDMV2) 7.3.2.4 BDM Global Page Index Register (BDMGPR) Register Global Address 0x7FFF08 R W Reset 7 6 5 4 3 2 1 0 BGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0 0 0 0 0 0 0 0 0 Figure 7-6. BDM Global Page Register (BDMGPR) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured Table 7-5.
PAGE 288
Chapter 7 Background Debug Module (S12XBDMV2) 7.4.1 Security If the user resets into special single chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip non-volatile memory (e.g. EEPROM and Flash EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set.
PAGE 289
Chapter 7 Background Debug Module (S12XBDMV2) 7.4.3 BDM Hardware Commands Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU on the SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control registers, and all external memory.
PAGE 290
Chapter 7 Background Debug Module (S12XBDMV2) Table 7-6. Hardware Commands (continued) Command WRITE_WORD Opcode (hex) C8 Data Description 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Must be aligned access. NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 7.4.
PAGE 291
Chapter 7 Background Debug Module (S12XBDMV2) Table 7-7. Firmware Commands Command(1) Opcode (hex) Data Description READ_NEXT(2) 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. READ_SP 67 16-bit data out Read stack pointer.
PAGE 292
Chapter 7 Background Debug Module (S12XBDMV2) 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For devices with external bus: The following cycle count information is only valid when the external wait function is not used (see wait bit of EBI sub-block). During an external wait the BDM can not steal a cycle.
PAGE 293
Chapter 7 Background Debug Module (S12XBDMV2) Hardware Read 8 Bits AT ~16 TC/Bit 16 Bits AT ~16 TC/Bit Command Address 150-BC Delay 16 Bits AT ~16 TC/Bit Data Next Command 150-BC Delay Hardware Write Command Address Next Command Data 48-BC DELAY Firmware Read Command Next Command Data 36-BC DELAY Firmware Write Command Data Next Command 76-BC Delay GO, TRACE Command Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Figure 7-7. BDM Command Structure 7.4.
PAGE 294
Chapter 7 Background Debug Module (S12XBDMV2) cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 7-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system.
PAGE 295
Chapter 7 Background Debug Module (S12XBDMV2) BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse High-Impedance High-Impedance High-Impedance Perceived Start of Bit Time R-C Rise BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 296
Chapter 7 Background Debug Module (S12XBDMV2) Figure 7-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it.
PAGE 297
Chapter 7 Background Debug Module (S12XBDMV2) compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. BDM Clock (Target MCU) 16 Cycles Target Transmits ACK Pulse High-Impedance High-Impedance 32 Cycles Speedup Pulse Minimum Delay From the BDM Command BKGD Pin Earliest Start of Next Bit 16th Tick of the Last Command Bit Figure 7-11.
PAGE 298
Chapter 7 Background Debug Module (S12XBDMV2) Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 7-11 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
PAGE 299
Chapter 7 Background Debug Module (S12XBDMV2) GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin.
PAGE 300
Chapter 7 Background Debug Module (S12XBDMV2) Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening.
PAGE 301
Chapter 7 Background Debug Module (S12XBDMV2) The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued.
PAGE 302
Chapter 7 Background Debug Module (S12XBDMV2) within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication.
PAGE 303
Chapter 7 Background Debug Module (S12XBDMV2) after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. 7.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued.
PAGE 304
Chapter 7 Background Debug Module (S12XBDMV2) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 305
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-1. Revision History Revision Number Revision Date Sections Affected V03.20 14 Sep 2007 8.3.2.7/8-317 - Clarified reserved State Sequencer encodings. V03.21 23 Oct 2007 8.4.2.2/8-329 8.4.2.4/8-330 - Added single databyte comparison limitation information - Added statement about interrupt vector fetches whilst tagging. V03.22 12 Nov 2007 8.4.5.2/8-334 8.4.5.5/8-341 - Removed LOOP1 tracing restriction NOTE. - Added pin reset effect NOTE. V03.
PAGE 306
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-2. Glossary Of Terms (continued) Term Definition Data Line 64-bit data entity CPU CPU12X module Tag Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 8.1.2 Overview The comparators monitor the bus activity of the CPU12X and XGATE. When a match occurs the control logic can trigger the state sequencer to a new state.
PAGE 307
Chapter 8 S12X Debug (S12XDBGV3) Module • • • XGATE S/W breakpoint request trigger independent of comparators TRIG Immediate software trigger independent of comparators Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 8.4.5.2.1) for change of flow definition.
PAGE 308
Chapter 8 S12X Debug (S12XDBGV3) Module 8.1.5 Block Diagram TAGS TAGHITS EXTERNAL TAGHI / TAGLO BREAKPOINT REQUESTS XGATE S/W BREAKPOINT REQUEST CPU12X & XGATE XGATE BUS COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL CPU12X BUS BUS INTERFACE SECURE MATCH1 TAG & TRIGGER CONTROL LOGIC TRIGGER STATE STATE SEQUENCER STATE MATCH2 MATCH3 TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 8-1. Debug Module Block Diagram 8.
PAGE 309
Chapter 8 S12X Debug (S12XDBGV3) Module Address Name Bit 7 6 0 TRIG 5 4 XGSBPE BDM 0 0 3 2 1 Bit 0 0x0020 DBGC1 R W 0x0021 DBGSR R W 0x0022 DBGTCR R W 0x0023 DBGC2 R W 0 0 0 0 0x0024 DBGTBH R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0025 DBGTBL R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0026 DBGCNT R W 0 0x0027 DBGSCRX 0 0 0 0 SC3 SC2 SC1 SC0 0x0027 DBGMFR R W R W 0 0 0 0 MC3 MC2 MC1 MC0 NDB TAG BRK
PAGE 310
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2 Register Descriptions This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]. 8.3.2.
PAGE 311
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-5. DBGC1 Field Descriptions (continued) Field 5 XGSBPE Description XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can request an CPU12X breakpoint depending on the state of this bit.
PAGE 312
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.2 Debug Status Register (DBGSR) Address: 0x0021 R 7 6 5 4 3 2 1 0 TBF EXTF 0 0 0 SSF2 SSF1 SSF0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset POR = Unimplemented or Reserved Figure 8-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 8-8. DBGSR Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed.
PAGE 313
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.3 Debug Trace Control Register (DBGTCR) Address: 0x0022 7 6 R TSOURCE W Reset 5 0 4 3 TRANGE 0 0 2 1 TRCMOD 0 0 0 TALIGN 0 0 0 Figure 8-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. Table 8-10.
PAGE 314
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-12. TRANGE Trace Range Encoding TRANGE Tracing Range 00 Trace from all addresses (No filter) 01 Trace only in address range from $00000 to Comparator D 10 Trace only in address range from Comparator C to $7FFFFF 11 Trace only in range from Comparator C to Comparator D Table 8-13. TRCMOD Trace Mode Bit Encoding TRCMOD Description 00 Normal 01 Loop1 10 Detail 11 Pure PC Table 8-14. TALIGN Trace Alignment Encoding 8.3.2.
PAGE 315
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-16. CDCM Encoding CDCM Description 00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match. 01 Match2 mapped to comparator C/D inside range....... Match3 disabled. 10 Match2 mapped to comparator C/D outside range....... Match3 disabled. 11 Reserved(1) 1. Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D Table 8-17. ABCM Encoding ABCM Description 00 Match0 mapped to comparator A match.....
PAGE 316
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 7 R 6 5 4 0 3 2 1 0 — 0 — 0 — 0 CNT W Reset POR 0 0 — 0 — 0 — 0 — 0 = Unimplemented or Reserved Figure 8-8. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 8-19. DBGCNT Field Descriptions Field Description 6–0 CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
PAGE 317
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.7 Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027).
PAGE 318
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-23. State1 Sequencer Next State Selection (continued) SC[3:0] 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Match2 triggers to State2....... Other matches have no effect Match2 triggers to State3....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3.......
PAGE 319
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-25. State2 —Sequencer Next State Selection (continued) SC[3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state3 Any match triggers to Final State Match3 triggers to State1....... Other matches have no effect Match3 triggers to State3....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Match0 triggers to State1.......
PAGE 320
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-27. State3 — Sequencer Next State Selection SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state2 Any match triggers to Final State Match0 triggers to State1....... Other matches have no effect Match0 triggers to State2....... Other matches have no effect Match0 triggers to Final State.......Match1 triggers to State1...
PAGE 321
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.8 Comparator Register Descriptions Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparators B and D consist of four register bytes (three address bus compare registers and a control register).
PAGE 322
Chapter 8 S12X Debug (S12XDBGV3) Module Write: If DBG not armed. See Table 8-29 for visible register encoding. The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 8-29. Table 8-29.
PAGE 323
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-30. DBGXCTL Field Descriptions (continued) Field Description 1 SRC Determines mapping of comparator to CPU12X or XGATE 0 The comparator is mapped to CPU12X buses 1 The comparator is mapped to XGATE address and data buses 0 COMPE Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled for state sequence triggers or tag generation Table 8-31 shows the effect for RWE and RW on the comparison conditions.
PAGE 324
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM) Address: 0x002A R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-16. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime. See Table 8-29 for visible register encoding. Write: If DBG not armed. See Table 8-29 for visible register encoding. Table 8-33.
PAGE 325
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.8.5 Debug Comparator Data High Register (DBGXDH) Address: 0x002C R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-18. Debug Comparator Data High Register (DBGXDH) Read: Anytime. See Table 8-29 for visible register encoding. Write: If DBG not armed. See Table 8-29 for visible register encoding. Table 8-35.
PAGE 326
Chapter 8 S12X Debug (S12XDBGV3) Module 8.3.2.8.7 Debug Comparator Data High Mask Register (DBGXDHM) Address: 0x002E R W Reset 7 6 5 4 3 2 1 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 8-20. Debug Comparator Data High Mask Register (DBGXDHM) Read: Anytime. See Table 8-29 for visible register encoding. Write: If DBG not armed. See Table 8-29 for visible register encoding. Table 8-37.
PAGE 327
Chapter 8 S12X Debug (S12XDBGV3) Module 8.4.1 S12XDBG Operation Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the CPU12X or the XGATE module. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU12X and XGATE. Comparators can be configured to monitor address and databus.
PAGE 328
Chapter 8 S12X Debug (S12XDBGV3) Module when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1).
PAGE 329
Chapter 8 S12X Debug (S12XDBGV3) Module NOTE Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.
PAGE 330
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-41. NDB and MASK bit dependency 8.4.2.4 NDB DBGxDHM[n] / DBGxDLM[n] Comment 0 0 Do not compare data bus bit. 0 1 Compare data bus bit. Match on equivalence. 1 0 Do not compare data bus bit. 1 1 Compare data bus bit. Match on difference. Range Comparisons When using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data and data mask registers.
PAGE 331
Chapter 8 S12X Debug (S12XDBGV3) Module When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR register and hence vector address can be modified. 8.4.3 Trigger Modes Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer.
PAGE 332
Chapter 8 S12X Debug (S12XDBGV3) Module this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the session. If breakpoints are enabled, a forced breakpoint request is issued immediately (end alignment) or when tracing has completed (begin or mid alignment). 8.4.3.6 Trigger Priorities In case of simultaneous triggers, the priority is resolved according to Table 8-42. The lower priority trigger is suppressed.
PAGE 333
Chapter 8 S12X Debug (S12XDBGV3) Module then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state.
PAGE 334
Chapter 8 S12X Debug (S12XDBGV3) Module 8.4.5.1 Trace Trigger Alignment Using the TALIGN bits (see Section 8.3.2.3) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered. The transition to Final State if End is selected signals the end of the tracing session.
PAGE 335
Chapter 8 S12X Debug (S12XDBGV3) Module • • Destination address of RTI, RTS, and RTC instructions. Vector address of interrupts, except for SWI and BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. COF addresses are defined as follows for the XGATE: • Source address of taken conditional branches • Destination address of indexed JAL instructions.
PAGE 336
Chapter 8 S12X Debug (S12XDBGV3) Module 8.4.5.2.2 Loop1 Mode Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions.
PAGE 337
Chapter 8 S12X Debug (S12XDBGV3) Module 2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry. XGATE and CPU12X COFs occur independently of each other and the profile of COFs for the two sources is totally different.
PAGE 338
Chapter 8 S12X Debug (S12XDBGV3) Module 8.4.5.3.1 Information Byte Organization The format of the control information byte is dependent upon the active trace mode as described below. In Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information. In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control information. In Detail Mode, CXINF contains the control information.
PAGE 339
Chapter 8 S12X Debug (S12XDBGV3) Module CPU12X Information Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CSD CVA 0 CDV 0 0 0 0 Figure 8-25. CPU12X Information Byte CINF Table 8-45. CINF Field Descriptions Field Description 7 CSD Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing.
PAGE 340
Chapter 8 S12X Debug (S12XDBGV3) Module Table 8-46. CXINF Field Descriptions (continued) Field Description 6 CSZ Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains valid information when tracing CPU12X activity in Detail Mode. 0 Word Access 1 Byte Access 5 CRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access.
PAGE 341
Chapter 8 S12X Debug (S12XDBGV3) Module The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1 and 0 of Table 8-43. The bytes containing invalid information (shaded in Table 8-43) are also read out. Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur. 8.4.5.5 Trace Buffer Reset State The Trace Buffer contents are not initialized by a system reset.
PAGE 342
Chapter 8 S12X Debug (S12XDBGV3) Module S12X tagging is disabled when the BDM becomes active. XGATE tagging is possible when the BDM is active. 8.4.6.1 External Tagging using TAGHI and TAGLO External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU12X opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into state0 when the tagged opcode reaches the execution stage of the instruction queue.
PAGE 343
Chapter 8 S12X Debug (S12XDBGV3) Module 8.4.7.1 XGATE Software Breakpoints The XGATE software breakpoint instruction BRK can request a CPU12X breakpoint, via the S12XDBG module. In this case, if the XGSBPE bit is set, the S12XDBG module immediately generates a forced breakpoint request to the CPU12X, the state sequencer is returned to state0 and tracing, if active, is terminated.
PAGE 344
Chapter 8 S12X Debug (S12XDBGV3) Module 8.4.7.3 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered. If a tracing session is selected by TSOURCE, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-48). If no tracing session is selected, breakpoints are requested immediately.
PAGE 345
Chapter 8 S12X Debug (S12XDBGV3) Module executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU12X flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code and DBG breakpoint could occur simultaneously. The CPU12X ensures that BDM requests have a higher priority than SWI requests.
PAGE 346
Chapter 8 S12X Debug (S12XDBGV3) Module MC9S12XE-Family Reference Manual Rev. 1.
PAGE 347
Chapter 9 Security (S12XE9SECV2) Table 9-1. Revision History Revision Number Revision Date V02.00 27 Aug 2004 - Reviewed and updated for S12XD architecture V02.01 21 Feb 2007 - Added S12XE, S12XF and S12XS architectures V02.02 19 Apr 2007 - Corrected statement about Backdoor key access via BDM on XE, XF, XS 9.1 Sections Affected Description of Changes Introduction This specification describes the function of the security mechanism in the S12XE chip family (9SEC).
PAGE 348
Chapter 9 Security (S12XE9SECV2) 9.1.2 Modes of Operation Table 9-2 gives an overview over availability of security relevant features in unsecure and secure modes. Table 9-2.
PAGE 349
Chapter 9 Security (S12XE9SECV2) Table 9-3. Backdoor Key Access Enable Bits KEYEN[1:0] Backdoor Key Access Enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) The meaning of the security bits SEC[1:0] is shown in Table 9-4. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode.
PAGE 350
Chapter 9 Security (S12XE9SECV2) 9.1.4.2 • • • • • Special Single Chip Mode (SS) BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled. Special single chip mode means BDM is active after reset.
PAGE 351
Chapter 9 Security (S12XE9SECV2) • • The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g.
PAGE 352
Chapter 9 Security (S12XE9SECV2) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 353
Chapter 10 XGATE (S12XGATEV3) Table 10-1. Revision History Revision Number V03.22 06 Oct 2005 V03.23 14 Dec 2005 V03.24 17 Jan 2006 10.1 Sections Affected Revision Date Description of Changes - Internal updates 10.9.2/10-463 - Updated code example - Internal updates Introduction The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories.
PAGE 354
Chapter 10 XGATE (S12XGATEV3) XGATE Channel ID A 7-bit identifier associated with an XGATE channel. In S12XE designs valid Channel IDs range from $0D to $78. XGATE Priority Level A priority ranging from 1 to 7 which is associated with an XGATE channel. The priority level of an XGATE channel is selected in the S12X_INT module. XGATE Register Bank A register bank consists of registers R1-R7, CCR and the PC. Each interrupt level is associated with one register bank.
PAGE 355
Chapter 10 XGATE (S12XGATEV3) • • • • • • Provides up to 108 XGATE channels, including 8 software triggered channels Interruptible thread execution Two register banks to support fast context switching between threads Hardware semaphores which are shared between the S12X_CPU and the XGATE module Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer Software error detection to catch erratic application code 10.1.3 Modes of Operation There are four run modes on S12XE devices.
PAGE 356
Chapter 10 XGATE (S12XGATEV3) 10.2 External Signal Description The XGATE module has no external pins. 10.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below in Figure 10-2.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level.
PAGE 357
Chapter 10 XGATE (S12XGATEV3) 0x0008 XGIF R 127 126 125 124 123 122 121 0 0 0 0 0 0 0 W 113 112 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R W XGIF_3F XGI
PAGE 358
Chapter 10 XGATE (S12XGATEV3) 15 14 13 0x0018 R XGSWTM W 0 0 0 0x001A R XGSEMM W 0 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 0 0 0 3 2 1 0 XGSWT[7:0] XGSWTM[7:0] 0 4 XGSEM[7:0] XGSEMM[7:0] 0x001C R Reserved W 0x001D XGCCR 0x001E XGPC R 0 0 0 0 W R XGN XGZ XGV XGC XGPC W 0x0020 R Reserved W 0x0021 R Reserved W 0x0022 XGR1 0x0024 XGR2 R R XGR2 W 0x0026 XGR3 W 0x0028 XGR4 W 0x002A XGR5 XGR1 W R XGR3 R XGR4 R XGR5 W 0x002C XGR6 R W 0x002E XGR7 W X
PAGE 359
Chapter 10 XGATE (S12XGATEV3) 10.3.1.1 XGATE Control Register (XGMCTL) All module level switches and flags are located in the XGATE Module Control Register Figure 10-3. Module Base +0x00000 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 XG SSM XG FACTM 0 0 R W XGEM Reset 0 XG XG FRZM DBGM 0 0 7 0 0 5 4 3 2 0 XG XGIEM SWEFM 0 6 XGE XGFRZ XGDBG XGSS XGFACT 0 0 0 0 0 0 1 0 XG SWEF XGIE 0 0 = Unimplemented or Reserved Figure 10-3.
PAGE 360
Chapter 10 XGATE (S12XGATEV3) Table 10-2. XGMCTL Field Descriptions (Sheet 2 of 3) Field 11 XGFACTM Description XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0".
PAGE 361
Chapter 10 XGATE (S12XGATEV3) Table 10-2. XGMCTL Field Descriptions (Sheet 3 of 3) Field 4 XGSS Description XGATE Single Step — This bit forces the execution of a single instruction.(1) Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed.
PAGE 362
Chapter 10 XGATE (S12XGATEV3) Module Base +0x0002 7 R 6 5 4 0 3 2 1 0 0 0 0 XGCHID[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 10-4. XGATE Channel ID Register (XGCHID) Read: Anytime Write: In Debug Mode1 Table 10-3. XGCHID Field Descriptions Field Description 6–0 Request Identifier — ID of the currently active channel XGCHID[6:0] 10.3.1.
PAGE 363
Chapter 10 XGATE (S12XGATEV3) this register to a channel priority level (non-zero value) selects the corresponding Initial Stack Pointer Registers XGISP74 or XGISP31 (see Table 10-6). Module Base +0x0005 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 1 XGISPSEL[1:0] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 10-6. XGATE Initial Stack Pointer Select Register (XGISPSEL) Read: Anytime Write: Anytime Table 10-5.
PAGE 364
Chapter 10 XGATE (S12XGATEV3) Table 10-7. XGISP74 Field Descriptions Field 15–1 XBISP74[15:1] 10.3.1.6 Description Initial Stack Pointer— The XGISP74 register holds the initial value of RISC core register R7, for threads of priority 7 to 4. XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31) The XGISP31 register is intended to point to the stack region that is used by XGATE channels of priority 3 to 1.
PAGE 365
Chapter 10 XGATE (S12XGATEV3) Table 10-9. XGVBR Field Descriptions Field Description 15–1 Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE XBVBR[15:1] memory map. 10.3.1.8 XGATE Channel Interrupt Flag Vector (XGIF) The XGATE Channel Interrupt Flag Vector (Figure 10-10) provides access to the interrupt flags of all channels. Each flag may be cleared by writing a "1" to its bit location. Refer to Section 10.5.
PAGE 366
Chapter 10 XGATE (S12XGATEV3) 63 R W 62 0 47 W Reset R W Reset R W Reset 60 59 58 57 56 55 54 53 52 51 50 49 48 XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 Reset R 61 0 46 0 45 0 44 0 43 0 42 0 41 0 40 0 39 0 38 0 37 0 36 0 35 0 34 0 33 0 32 XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 0 0 0 0 0 0
PAGE 367
Chapter 10 XGATE (S12XGATEV3) NOTE Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0]) 10.3.1.9 XGATE Software Trigger Register (XGSWT) The eight software triggers of the XGATE module can be set and cleared through the XGATE Software Trigger Register (Figure 10-11).
PAGE 368
Chapter 10 XGATE (S12XGATEV3) Table 10-11. XGSWT Field Descriptions Field Description 15–8 Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access. Read: These bits will always read "0".
PAGE 369
Chapter 10 XGATE (S12XGATEV3) Table 10-12. XGSEM Field Descriptions Field Description 15–8 Semaphore Mask — These bits control the write access to the XGSEM bits. XGSEMM[7:0] Read: These bits will always read "0". Write: 0 Disable write access to the XGSEM in the same bus cycle 1 Enable write access to the XGSEM in the same bus cycle 7–0 XGSEM[7:0] Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU.
PAGE 370
Chapter 10 XGATE (S12XGATEV3) 10.3.1.12 XGATE Program Counter Register (XGPC) The XGPC register (Figure 10-14) provides access to the RISC core’s program counter. Module Base +0x0001E 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGPC W Reset 7 0 0 0 0 0 0 0 0 Figure 10-14. XGATE Program Counter Register (XGPC) Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-14.
PAGE 371
Chapter 10 XGATE (S12XGATEV3) 10.3.1.14 XGATE Register 2 (XGR2) The XGR2 register (Figure 10-16) provides access to the RISC core’s register 2. Module Base +0x00024 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR2 W Reset 7 0 0 0 0 0 0 0 0 Figure 10-16. XGATE Register 2 (XGR2) Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-16.
PAGE 372
Chapter 10 XGATE (S12XGATEV3) 10.3.1.16 XGATE Register 4 (XGR4) The XGR4 register (Figure 10-18) provides access to the RISC core’s register 4. Module Base +0x00028 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR4 W Reset 7 0 0 0 0 0 0 0 0 Figure 10-18. XGATE Register 4 (XGR4) Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-18.
PAGE 373
Chapter 10 XGATE (S12XGATEV3) 10.3.1.18 XGATE Register 6 (XGR6) The XGR6 register (Figure 10-20) provides access to the RISC core’s register 6. Module Base +0x0002C 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR6 W Reset 7 0 0 0 0 0 0 0 0 Figure 10-20. XGATE Register 6 (XGR6) Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Table 10-20.
PAGE 374
Chapter 10 XGATE (S12XGATEV3) Section for information on how to select priority levels for XGATE threads. Low priority threads (interrupt levels 1 to 3) can be interrupted by high priority threads (interrupt levels 4 to 7). High priority threads are not interruptible. The register content of an interrupted thread is maintained and restored by the XGATE hardware. To signal the completion of a task the XGATE is able to send interrupts to the S12X_CPU. Each XGATE channel has its own interrupt vector.
PAGE 375
Chapter 10 XGATE (S12XGATEV3) The programmer’s model of the XGATE RISC core is shown in Figure 10-22. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional eighth register (R0) is tied to the value “$0000”. Registers R1 and R7 have additional functionality. R1 is preloaded with the initial data pointer of the channel’s service request vector (see Figure 10-23).
PAGE 376
Chapter 10 XGATE (S12XGATEV3) XGVBR +$0000 unused Code +$0024 Channel $09 Initial Program Counter Channel $09 Initial Data Pointer +$0028 Channel $0A Initial Program Counter Data Channel $0A Initial Data Pointer +$002C Channel $0B Initial Program Counter Channel $0B Initial Data Pointer +$0030 Channel $0C Initial Program Counter Code Channel $0C Initial Data Pointer +$01E0 Channel $78 Initial Program Counter Data Channel $78 Initial Data Pointer Figure 10-23. XGATE Vector Block 10.4.
PAGE 377
Chapter 10 XGATE (S12XGATEV3) set_xgsem: clr_xgsem: ssem: csem: 1 is written to XGSEM[n] (and 1 is written to XGSEMM[n]) 0 is written to XGSEM[n] (and 1 is written to XGSEMM[n]) Executing SSEM instruction (on semaphore n) Executing CSEM instruction (on semaphore n) clr_xgsem csem LOCKED BY S12X_CPU LOCKED BY XGATE clr_xgsem csem ssem & set_xgsem ssem UNLOCKED ssem & set_xgsem Figure 10-24.
PAGE 378
Chapter 10 XGATE (S12XGATEV3) S12X_CPU XGATE ......... ......... 1 ⇒ XGSEM[n] SSEM XGSEM[n] 1? BCC? critical code sequence 0 ⇒ XGSEM[n] ......... critical code sequence CSEM ......... Figure 10-25. Algorithm for Locking and Releasing Semaphores 10.4.5 Software Error Detection Upon detecting an error condition caused by erratic application code, the XGATE module will immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU.
PAGE 379
Chapter 10 XGATE (S12XGATEV3) 10.5 10.5.1 Interrupts Incoming Interrupt Requests XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the device overview. 10.5.
PAGE 380
Chapter 10 XGATE (S12XGATEV3) • • Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly. Write accesses to the XGCHID register and the XGCHPL register XGATE threads can be initiated and terminated through a 16 write access to the XGCHID and the XGCHPL register or through a 8 bit write access to the XGCHID register. Detailed operation is shown in Table 10-22.
PAGE 381
Chapter 10 XGATE (S12XGATEV3) Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter debug mode upon completion of the current instruction. NOTE After writing to the XGDBG bit the XGATE will not immediately enter debug mode. Depending on the instruction that is executed at this time there may be a delay of several clock cycles. The XGDBG will read "0" until debug mode is entered. 2.
PAGE 382
Chapter 10 XGATE (S12XGATEV3) 10.8 Instruction Set 10.8.1 Addressing Modes For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all operations must have one of the eight general purpose registers R0 … R7 as their source as well their destination. All word accesses must work with a word aligned address, that is A[0] = 0! 10.8.1.1 Naming Conventions RD RD.L RD.H RS, RS1, RS2 RS.L, RS1.L, RS2.L RS.H, RS1.H, RS2.
PAGE 383
Chapter 10 XGATE (S12XGATEV3) 10.8.1.3 Immediate 3-Bit Wide (IMM3) Operands for immediate mode instructions are included in the instruction stream and are fetched into the instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an immediate addressing mode operand. This address mode is used for semaphore instructions. Examples: CSEM SSEM 10.8.1.
PAGE 384
Chapter 10 XGATE (S12XGATEV3) 10.8.1.8 Dyadic Addressing (DYA) In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated.
PAGE 385
Chapter 10 XGATE (S12XGATEV3) 10.8.1.13 Index Register plus Register Offset (IDR) For load and store instructions (RS, RI) provides a variable offset in a register. Examples: LDB STW R4,(R1,R2) R4,(R1,R2) ; loads a byte from (R1+R2) into R4 ; stores R4 as a word to (R1+R2) 10.8.1.14 Index Register plus Register Offset with Post-increment (IDR+) [RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory.
PAGE 386
Chapter 10 XGATE (S12XGATEV3) 10.8.2.2 Logic and Arithmetic Instructions All logic and arithmetic instructions support the 8 bit immediate addressing mode (IMM8: RD = RD ∗ #IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2). All arithmetic is considered as signed, sign, overflow, zero and carry flag will be updated. The carry will not be affected for logical operations. ADDL ANDH R2,#1 R4,#$FE ; increment R2 ; R4.H = R4.
PAGE 387
Chapter 10 XGATE (S12XGATEV3) 10.8.2.5 Bit Field Operations This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit.
PAGE 388
Chapter 10 XGATE (S12XGATEV3) Table 10-23.
PAGE 389
Chapter 10 XGATE (S12XGATEV3) ADC ADC Add with Carry Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions.
PAGE 390
Chapter 10 XGATE (S12XGATEV3) ADD ADD Add without Carry Operation RS1 + RS2 ⇒ RD RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #IMM16[15:8]) Performs a 16 bit addition and stores the result in the destination register RD. NOTE When using immediate addressing mode (ADD RD, #IMM16), the V-flag and the C-Flag of the first instruction (ADDL RD, #IMM16[7:0]) are not considered by the second instruction (ADDH RD, #IMM16[15:8]). ⇒ Don’t rely on the V-Flag if RD + IMM16[7:0] ≥ 215.
PAGE 391
Chapter 10 XGATE (S12XGATEV3) ADDH Add Immediate 8 bit Constant (High Byte) ADDH Operation RD + IMM8:$00 ⇒ RD Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16 bit immediate addition.
PAGE 392
Chapter 10 XGATE (S12XGATEV3) ADDL Add Immediate 8 bit Constant (Low Byte) ADDL Operation RD + $00:IMM8 ⇒ RD Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition in conjunction with the ADDH instruction. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise.
PAGE 393
Chapter 10 XGATE (S12XGATEV3) AND AND Logical AND Operation RS1 & RS2 ⇒ RD RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD. NOTE When using immediate addressing mode (AND RD, #IMM16), the Z-flag of the first instruction (ANDL RD, #IMM16[7:0]) is not considered by the second instruction (ANDH RD, #IMM16[15:8]). ⇒ Don’t rely on the Z-Flag.
PAGE 394
Chapter 10 XGATE (S12XGATEV3) ANDH Logical AND Immediate 8 bit Constant (High Byte) ANDH Operation RD.H & IMM8 ⇒ RD.H Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 395
Chapter 10 XGATE (S12XGATEV3) ANDL Logical AND Immediate 8 bit Constant (Low Byte) ANDL Operation RD.L & IMM8 ⇒ RD.L Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 396
Chapter 10 XGATE (S12XGATEV3) ASR ASR Arithmetic Shift Right Operation n b15 RD C n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is equal to 0.
PAGE 397
Chapter 10 XGATE (S12XGATEV3) BCC BCC Branch if Carry Cleared (Same as BHS) Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BCC REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 398
Chapter 10 XGATE (S12XGATEV3) BCS BCS Branch if Carry Set (Same as BLO) Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BCS REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 399
Chapter 10 XGATE (S12XGATEV3) BEQ BEQ Branch if Equal Operation If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 1. CCR Effect N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BEQ REL9 Address Mode REL9 Machine Code 0 0 1 0 0 1 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 400
Chapter 10 XGATE (S12XGATEV3) BFEXT BFEXT Bit Field Extract Operation RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)] w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD. The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
PAGE 401
Chapter 10 XGATE (S12XGATEV3) BFFO BFFO Bit Field Find First One Operation FirstOne(RS) ⇒ RD; Searches the first “1” in register RS (from MSB to LSB) and writes the bit position into the destination register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be cleared and the carry flag will be set. This is used to distinguish a “1” in position 0 versus no “1” in the whole RS register at all. CCR Effects N Z V C 0 ∆ 0 ∆ N: 0; cleared.
PAGE 402
Chapter 10 XGATE (S12XGATEV3) BFINS BFINS Bit Field Insert Operation RS1[w:0] ⇒ RD[(w+o):o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD starting at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to clear bits.
PAGE 403
Chapter 10 XGATE (S12XGATEV3) BFINSI BFINSI Bit Field Insert and Invert Operation !RS1[w:0] ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD starting at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits.
PAGE 404
Chapter 10 XGATE (S12XGATEV3) BFINSX BFINSX Bit Field Insert and XNOR Operation !(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back to RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits.
PAGE 405
Chapter 10 XGATE (S12XGATEV3) BGE BGE Branch if Greater than or Equal to Zero Operation If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≥ RS2: SUB BGE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BGE REL9 Address Mode REL9 Machine Code 0 0 1 1 0 1 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 406
Chapter 10 XGATE (S12XGATEV3) BGT BGT Branch if Greater than Zero Operation If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 > RS2: SUB BGT R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BGT REL9 Address Mode REL9 Machine Code 0 0 1 1 1 0 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 407
Chapter 10 XGATE (S12XGATEV3) BHI BHI Branch if Higher Operation If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 > RS2: SUB BHI R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BHI REL9 Address Mode REL9 Machine Code 0 0 1 1 0 0 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 408
Chapter 10 XGATE (S12XGATEV3) BHS BHS Branch if Higher or Same (Same as BCC) Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≥ RS2: SUB BHS R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BHS REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 409
Chapter 10 XGATE (S12XGATEV3) BITH BITH Bit Test Immediate 8 bit Constant (High Byte) Operation RD.H & IMM8 ⇒ NONE Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant. Only the condition code flags get updated, but no result is written back. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 410
Chapter 10 XGATE (S12XGATEV3) BITL BITL Bit Test Immediate 8 bit Constant (Low Byte) Operation RD.L & IMM8 ⇒ NONE Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant. Only the condition code flags get updated, but no result is written back. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 411
Chapter 10 XGATE (S12XGATEV3) BLE BLE Branch if Less or Equal to Zero Operation If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≤ RS2: SUB BLE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLE REL9 Address Mode REL9 Machine Code 0 0 1 1 1 0 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 412
Chapter 10 XGATE (S12XGATEV3) BLO BLO Branch if Carry Set (Same as BCS) Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 < RS2: SUB BLO R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLO REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 413
Chapter 10 XGATE (S12XGATEV3) BLS BLS Branch if Lower or Same Operation If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≤ RS2: SUB BLS R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLS REL9 Address Mode REL9 Machine Code 0 0 1 1 0 0 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 414
Chapter 10 XGATE (S12XGATEV3) BLT BLT Branch if Lower than Zero Operation If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 < RS2: SUB BLT R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLT REL9 Address Mode REL9 Machine Code 0 0 1 1 0 1 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 415
Chapter 10 XGATE (S12XGATEV3) BMI BMI Branch if Minus Operation If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the sign flag and branches if N = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BMI REL9 Address Mode REL9 Machine Code 0 0 1 0 1 0 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 416
Chapter 10 XGATE (S12XGATEV3) BNE BNE Branch if Not Equal Operation If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BNE REL9 Address Mode REL9 Machine Code 0 0 1 0 0 1 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 417
Chapter 10 XGATE (S12XGATEV3) BPL BPL Branch if Plus Operation If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BPL REL9 Address Mode REL9 Machine Code 0 0 1 0 1 0 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 418
Chapter 10 XGATE (S12XGATEV3) BRA BRA Branch Always Operation PC + $0002 + (REL10 << 1) ⇒ PC Branches always. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BRA REL10 Address Mode REL10 Machine Code 0 0 1 1 1 1 Cycles REL10 PP MC9S12XE-Family Reference Manual Rev. 1.
PAGE 419
Chapter 10 XGATE (S12XGATEV3) BRK BRK Break Operation Put XGATE into Debug Mode (see Section 10.6.1.0.1, “Entering Debug Mode”) and signals a software breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). NOTE It is not possible to single step over a BRK instruction. This instruction does not advance the program counter. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 420
Chapter 10 XGATE (S12XGATEV3) BVC BVC Branch if Overflow Cleared Operation If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BVC REL9 Address Mode REL9 Machine Code 0 0 1 0 1 1 0 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 421
Chapter 10 XGATE (S12XGATEV3) BVS BVS Branch if Overflow Set Operation If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BVS REL9 Address Mode REL9 Machine Code 0 0 1 0 1 1 1 Cycles REL9 PP/P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 422
Chapter 10 XGATE (S12XGATEV3) CMP CMP Compare Operation RS1 – RS2 ⇒ NONE (translates to SUB R0, RS1, RS2) RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8]) Subtracts two 16 bit values and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 423
Chapter 10 XGATE (S12XGATEV3) CMPL Compare Immediate 8 bit Constant (Low Byte) CMPL Operation RS.L – IMM8 ⇒ NONE, only condition code flags get updated Subtracts the 8 bit constant IMM8 contained in the instruction code from the low byte of the source register RS.L using binary subtraction and updates the condition code register accordingly. Remark: There is no equivalent operation using triadic addressing.
PAGE 424
Chapter 10 XGATE (S12XGATEV3) COM COM One’s Complement Operation ~RS ⇒ RD (translates to XNOR RD, R0, RS) ~RD ⇒ RD (translates to XNOR RD, R0, RD) Performs a one’s complement on a general purpose register. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
PAGE 425
Chapter 10 XGATE (S12XGATEV3) CPC CPC Compare with Carry Operation RS1 – RS2 - C ⇒ NONE (translates to SBC R0, RS1, RS2) Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary subtraction and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 426
Chapter 10 XGATE (S12XGATEV3) CPCH Compare Immediate 8 bit Constant with Carry (High Byte) CPCH Operation RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of the source register RD using binary subtraction and updates the condition code register accordingly.
PAGE 427
Chapter 10 XGATE (S12XGATEV3) CSEM CSEM Clear Semaphore Operation Unlocks a semaphore that was locked by the RISC core. In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 428
Chapter 10 XGATE (S12XGATEV3) CSL CSL Logical Shift Left with Carry Operation n C RD C C C C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is equal to 0.
PAGE 429
Chapter 10 XGATE (S12XGATEV3) CSR CSR Logical Shift Right with Carry Operation n C C C C RD C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is equal to 0.
PAGE 430
Chapter 10 XGATE (S12XGATEV3) JAL JAL Jump and Link Operation PC + $0002 ⇒ RD; RD ⇒ PC Jumps to the address stored in RD and saves the return address in RD. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form JAL RD Address Mode MON Machine Code 0 0 0 0 0 RD 1 1 Cycles 1 1 0 1 1 0 PP MC9S12XE-Family Reference Manual Rev. 1.
PAGE 431
Chapter 10 XGATE (S12XGATEV3) LDB LDB Load Byte from Memory (Low Byte) Operation M[RB, #OFFS5] M[RB, RI] M[RB, RI] RI-1 ⇒ RD.L; ⇒ RD.L; ⇒ RD.L; ⇒ RI; $00 ⇒ RD.H $00 ⇒ RD.H $00 ⇒ RD.H; M[RS, RI] ⇒ RD.L; RI+1 ⇒ RI;1 $00 ⇒ RD.H Loads a byte from memory into the low byte of register RD. The high byte is cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 432
Chapter 10 XGATE (S12XGATEV3) LDH LDH Load Immediate 8 bit Constant (High Byte) Operation IMM8 ⇒ RD.H; Loads an 8 bit immediate constant into the high byte of register RD. The low byte is not affected. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form LDH RD, #IMM8 Address Mode IMM8 Machine Code 1 1 1 1 1 RD Cycles IMM8 P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 433
Chapter 10 XGATE (S12XGATEV3) LDL LDL Load Immediate 8 bit Constant (Low Byte) Operation IMM8 ⇒ RD.L; $00 ⇒ RD.H Loads an 8 bit immediate constant into the low byte of register RD. The high byte is cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form LDL RD, #IMM8 Address Mode IMM8 Machine Code 1 1 1 1 0 RD Cycles IMM8 P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 434
Chapter 10 XGATE (S12XGATEV3) LDW LDW Load Word from Memory Operation M[RB, #OFFS5] M[RB, RI] M[RB, RI] RI-2 IMM16 ⇒ RD ⇒ RD ⇒ RD; RI+2 ⇒ RI1 ⇒ RI; M[RS, RI] ⇒ RD ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16 bit value into the register RD. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 435
Chapter 10 XGATE (S12XGATEV3) LSL LSL Logical Shift Left Operation n C RD 0 0 0 0 n bits n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
PAGE 436
Chapter 10 XGATE (S12XGATEV3) LSR LSR Logical Shift Right Operation n 0 0 0 0 RD C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
PAGE 437
Chapter 10 XGATE (S12XGATEV3) MOV MOV Move Register Content Operation RS ⇒ RD (translates to OR RD, R0, RS) Copies the content of RS to RD. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form MOV RD, RS Address Mode TRI Machine Code 0 0 0 1 0 RD 0 0 Cycles 0 RS 1 0 P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 438
Chapter 10 XGATE (S12XGATEV3) NEG NEG Two’s Complement Operation –RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’s complement on a general purpose register. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 439
Chapter 10 XGATE (S12XGATEV3) NOP NOP No Operation Operation No Operation for one cycle. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form NOP Address Mode INH Machine Code 0 0 0 0 0 0 0 1 0 0 Cycles 0 0 0 0 0 0 P MC9S12XE-Family Reference Manual Rev. 1.
PAGE 440
Chapter 10 XGATE (S12XGATEV3) OR OR Logical OR Operation RS1 | RS2 ⇒ RD RD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16 bit values and stores the result in the destination register RD. NOTE When using immediate addressing mode (OR RD, #IMM16), the Z-flag of the first instruction (ORL RD, #IMM16[7:0]) is not considered by the second instruction (ORH RD, #IMM16[15:8]). ⇒ Don’t rely on the Z-Flag.
PAGE 441
Chapter 10 XGATE (S12XGATEV3) ORH ORH Logical OR Immediate 8 bit Constant (High Byte) Operation RD.H | IMM8 ⇒ RD.H Performs a bit wise logical OR between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 442
Chapter 10 XGATE (S12XGATEV3) ORL ORL Logical OR Immediate 8 bit Constant (Low Byte) Operation RD.L | IMM8 ⇒ RD.L Performs a bit wise logical OR between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
PAGE 443
Chapter 10 XGATE (S12XGATEV3) PAR PAR Calculate Parity Operation Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise it will be cleared. CCR Effects N Z V C 0 ∆ 0 ∆ N: Z: V: C: 0; cleared. Set if RD is $0000; cleared otherwise. 0; cleared. Set if the number of ones in the register RD is odd; cleared otherwise.
PAGE 444
Chapter 10 XGATE (S12XGATEV3) ROL ROL Rotate Left Operation RD n bits n = RS or IMM4 Rotates the bits in register RD n positions to the left. The lower n bits of the register RD are filled with the upper n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored.
PAGE 445
Chapter 10 XGATE (S12XGATEV3) ROR ROR Rotate Right Operation RD n bits n = RS or IMM4 Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored.
PAGE 446
Chapter 10 XGATE (S12XGATEV3) RTS RTS Return to Scheduler Operation Terminates the current thread of program execution. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form RTS Address Mode INH Machine Code 0 0 0 0 0 0 1 0 0 0 Cycles 0 0 0 0 0 0 PA MC9S12XE-Family Reference Manual Rev. 1.
PAGE 447
Chapter 10 XGATE (S12XGATEV3) SBC SBC Subtract with Carry Operation RS1 - RS2 - C ⇒ RD Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using binary subtraction and stores the result in the destination register RD. Also the zero flag is carried forward from the previous operation allowing 32 and more bit subtractions.
PAGE 448
Chapter 10 XGATE (S12XGATEV3) SEX SEX Sign Extend Byte to Word Operation The result in RD is the 16 bit sign extended representation of the original two’s complement number in the low byte of RD.L. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
PAGE 449
Chapter 10 XGATE (S12XGATEV3) SIF SIF Set Interrupt Flag Operation Sets the interrupt flag of an XGATE channel (XGIF). This instruction supports two source forms. If inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the monadic address form is used, the interrupt flag associated with the channel id number contained in RS[6:0] is set. The content of RS[15:7] is ignored. NOTE Interrupt flags of reserved channels (see Device User Guide) can’t be set.
PAGE 450
Chapter 10 XGATE (S12XGATEV3) SSEM SSEM Set Semaphore Operation Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag: 1 = Semaphore is locked by the RISC core 0 = Semaphore is locked by the S12X_CPU In monadic address mode, bits RS[2:0] select the semaphore to be set. CCR Effects N Z V C — — — ∆ N: Z: V: C: Not affected. Not affected. Not affected. Set if semaphore is locked by the RISC core; cleared otherwise.
PAGE 451
Chapter 10 XGATE (S12XGATEV3) STB STB Store Byte to Memory (Low Byte) Operation RS.L ⇒ M[RB, #OFFS5] RS.L ⇒ M[RB, RI] RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]1 Stores the low byte of register RS to memory. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 452
Chapter 10 XGATE (S12XGATEV3) STW STW Store Word to Memory Operation RS ⇒ M[RB, #OFFS5] RS ⇒ M[RB, RI] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI]1 Stores the content of register RS to memory. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
PAGE 453
Chapter 10 XGATE (S12XGATEV3) SUB SUB Subtract without Carry Operation RS1 – RS2 ⇒ RD RD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8]) Subtracts two 16 bit values and stores the result in the destination register RD. NOTE When using immediate addressing mode (SUB RD, #IMM16), the V-flag and the C-Flag of the first instruction (SUBL RD, #IMM16[7:0]) are not considered by the second instruction (SUBH RD, #IMM16[15:8]). ⇒ Don’t rely on the V-Flag if RD - IMM16[7:0] < −215.
PAGE 454
Chapter 10 XGATE (S12XGATEV3) SUBH Subtract Immediate 8 bit Constant (High Byte) SUBH Operation RD – IMM8:$00 ⇒ RD Subtracts a signed immediate 8 bit constant from the content of high byte of register RD and using binary subtraction and stores the result in the high byte of destination register RD. This instruction can be used after an SUBL for a 16 bit immediate subtraction.
PAGE 455
Chapter 10 XGATE (S12XGATEV3) SUBL Subtract Immediate 8 bit Constant (Low Byte) SUBL Operation RD – $00:IMM8 ⇒ RD Subtracts an immediate 8 bit constant from the content of register RD using binary subtraction and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
PAGE 456
Chapter 10 XGATE (S12XGATEV3) TFR TFR Transfer from and to Special Registers Operation TFR RD,CCR: CCR ⇒ RD[3:0]; 0 ⇒ RD[15:4] TFR CCR,RD: RD[3:0] ⇒ CCR TFR RD,PC: PC+4 ⇒ RD Transfers the content of one RISC core register to another. The TFR RD,PC instruction can be used to implement relative subroutine calls. Example: RETADDR SUBR TFR BRA ... ...
PAGE 457
Chapter 10 XGATE (S12XGATEV3) TST TST Test Register Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
PAGE 458
Chapter 10 XGATE (S12XGATEV3) XNOR XNOR Logical Exclusive NOR Operation ~(RS1 ^ RS2) ⇒ RD ~(RD ^ IMM16)⇒ RD (translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0]) Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination register RD. Remark: Using R0 as a source registers will calculate the one’s complement of the other source register. Using R0 as both source operands will fill RD with $FFFF.
PAGE 459
Chapter 10 XGATE (S12XGATEV3) XNORH Logical Exclusive NOR Immediate 8 bit Constant (High Byte) XNORH Operation ~(RD.H ^ IMM8) ⇒ RD.H Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared.
PAGE 460
Chapter 10 XGATE (S12XGATEV3) XNORL Logical Exclusive NOR Immediate 8 bit Constant (Low Byte) XNORL Operation ~(RD.L ^ IMM8) ⇒ RD.L Performs a bit wise logical exclusive NOR between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared.
PAGE 461
Chapter 10 XGATE (S12XGATEV3) 10.8.6 Instruction Coding Table 10-24 summarizes all XGATE instructions in the order of their machine coding. Table 10-24.
PAGE 462
Chapter 10 XGATE (S12XGATEV3) Table 10-24.
PAGE 463
Chapter 10 XGATE (S12XGATEV3) Table 10-24. Instruction Set Summary (Sheet 3 of 3) Functionality Arithmetic Immediate Instructions SUBL RD, #IMM8 SUBH RD, #IMM8 CMPL RS, #IMM8 CPCH RS, #IMM8 ADDL RD, #IMM8 ADDH RD, #IMM8 LDL RD, #IMM8 LDH RD, #IMM8 10.9 10.9.
PAGE 464
Chapter 10 XGATE (S12XGATEV3) SCI_VEC EQU $D6 ;SCI vector number INT_REGS INT_CFADDR INT_CFDATA RQST EQU EQU EQU EQU $0120 INT_REGS+$07 INT_REGS+$08 $80 ;S12X_INT register space ;Interrupt Configuration Address Register ;Interrupt Configuration Data Registers ;RQST bit mask XGATE_REGS XGMCTL XGMCTL_CLEAR XGMCTL_ENABLE XGCHID XGISPSEL XGVBR XGIF XGSWT XGSEM EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $0380 XGATE_REGS+$00 $FA02 $8282 XGATE_REGS+$02 XGATE_REGS+$05 XGATE_REGS+$06 XGATE_REGS+$08 XGATE_REG
PAGE 465
Chapter 10 XGATE (S12XGATEV3) ;########################################### ;# INITIALIZE S12XE CORE # ;########################################### SEI MOVB #(RAM_START_GLOB>>12), RPAGE ;set RAM page INIT_SCI INIT_INT INIT_XGATE INIT_XGATE_BUSY_LOOP ;########################################### ;# INITIALIZE SCI # ;########################################### MOVW #(BUS_FREQ_HZ/(16*9600)), SCIBDH;set baud rate MOVB #(TIE|TE), SCICR2;enable tx buffer empty interrupt ;#######################################
PAGE 466
Chapter 10 XGATE (S12XGATEV3) MOVW MOVW MOVW CPX BLS START_XGATE ;########################################### ;# START XGATE # ;########################################### MOVW #XGMCTL_ENABLE, XGMCTL ;enable XGATE BRA * ;########################################### ;# DUMMY INTERRUPT SERVICE ROUTINE # ;########################################### RTI DUMMY_ISR XGATE_DATA_FLASH XGATE_DATA_SCI XGATE_DATA_IDX XGATE_DATA_MSG XGATE_CODE_FLASH XGATE_CODE_DONE XGATE_CODE_FLASH_END XGATE_DUMMY_ISR_XG 10.9.
PAGE 467
Chapter 10 XGATE (S12XGATEV3) Interrupt Priorities 7 to 4 (XGISP74)”) and one for threads of priority level 3 to 1 (refer to Section 10.3.1.6, “XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)”). MC9S12XE-Family Reference Manual Rev. 1.
PAGE 468
Chapter 10 XGATE (S12XGATEV3) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 469
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-1. Revision History Revision Number Revision Date Sections Affected V01.03 1 Sep. 2008 Table 11-14 V01.04 20 Nov. 2008 V01.05 19. Sep 2009 11.5.1/11-495 V01.06 18. Sep 2012 Table 11-14 11.5.1 11.1 Description of Changes added 100MHz example for PLL 11.3.2.4/11-475 S12XECRG Flags Register: corrected address to Module Base + 0x0003 Modified Note below Table 11-17.
PAGE 470
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) • — Illegal address reset — COP reset — Loss of clock reset — External pin reset Real-Time Interrupt (RTI) 11.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the S12XECRG. • Run Mode All functional parts of the S12XECRG are running during normal Run Mode.
PAGE 471
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Illegal Address Reset S12X_MMC Power on Reset Voltage Regulator Low Voltage Reset ICRG RESET CM Fail Clock Monitor OSCCLK EXTAL Oscillator XTAL COP Timeout XCLKS Reset Generator Clock Quality Checker System Reset Bus Clock Core Clock COP RTI Oscillator Clock Registers PLLCLK VDDPLL IPLL VSSPLL Real Time Interrupt Clock and Reset Control PLL Lock Interrupt Self Clock Mode Interrupt Figure 11-1. Block diagram of S12XECRG 11.
PAGE 472
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.3 Memory Map and Registers This section provides a detailed description of all registers accessible in the S12XECRG. 11.3.1 Module Memory Map Figure 11-2 gives an overview on all S12XECRG registers.
PAGE 473
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.3.2 Register Descriptions This section describes in address order all the S12XECRG registers and their individual bits. 11.3.2.1 S12XECRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range. Module Base + 0x0000 7 6 5 4 3 2 1 0 0 0 0 R VCOFRQ[1:0] SYNDIV[5:0] W Reset 0 0 0 0 0 Figure 11-3.
PAGE 474
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.3.2.2 S12XECRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the IPLL multiplier steps. Module Base + 0x0001 7 6 5 4 3 2 1 0 0 0 0 R REFFRQ[1:0] REFDIV[5:0] W Reset 0 0 0 0 0 Figure 11-4. S12XECRG Reference Divider Register (REFDV) Read: Anytime Write: Anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit.
PAGE 475
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Module Base + 0x0002 R 7 6 5 0 0 0 4 3 2 1 0 0 0 2 1 0 ILAF SCMIF 0 0 POSTDIV[4:0] W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. S12XECRG Post Divider Register (POSTDIV) Read: Anytime Write: Anytime except if PLLSEL = 1 f VCO f PLL = -------------------------------------( 2xPOSTDIV ) NOTE If POSTDIV = $00 then fPLL is identical to fVCO (divide by one). 11.3.2.
PAGE 476
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-4. CRGFLG Field Descriptions Field Description 7 RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. 6 PORF Power on Reset Flag — PORF is set to 1 when a power on reset occurs.
PAGE 477
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Read: Anytime Write: Anytime Table 11-5. CRGINT Field Descriptions Field 7 RTIE Description Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. 4 LOCKIE Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 SCMIE Self Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled.
PAGE 478
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-6. CLKSEL Field Descriptions Field 7 PLLSEL 6 PSTP Description PLL Select Bit Write: Anytime. Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
PAGE 479
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Read: Anytime Write: Refer to each bit for individual write conditions Table 11-7. PLLCTL Field Descriptions Field Description 7 CME Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock Mode. Note: Operating with CME=0 will not detect any loss of clock.
PAGE 480
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-8. FM Amplitude selection FM1 11.3.2.8 FM Amplitude / fVCO Variation FM0 0 0 FM off 0 1 ±1% 1 0 ±2% 1 1 ±4% S12XECRG RTI Control Register (RTICTL) This register selects the timeout period for the Real Time Interrupt. Module Base + 0x0007 7 6 5 4 3 2 1 0 RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 0 0 0 0 0 0 0 0 R W Reset Figure 11-10.
PAGE 481
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-10.
PAGE 482
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-11. RTI Frequency Divide Rates for RTDEC=1 RTR[6:4] = RTR[3:0] 000 (1x103) 001 (2x103) 010 (5x103) 011 (10x103) 100 (20x103) 101 (50x103) 110 (100x103) 111 (200x103) 0110 (÷7) 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1.4x106 0111 (÷8) 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1.6x106 1000 (÷9) 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1.
PAGE 483
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) The COP time-out period is restarted if one these two conditions is true: 1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. or 2. Changing RSBCK bit from “0” to “1”. Table 11-12. COPCTL Field Descriptions Field Description 7 WCOP Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period.
PAGE 484
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-13. COP Watchdog Rates(1) CR2 CR1 OSCCLK Cycles to Timeout CR0 1 1 1 2 24 1. OSCCLK cycles are referenced from the previous COP time-out reset (writing $55/$AA to the ARMCOP register) 11.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the S12XECRG’s functionality.
PAGE 485
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Write: Only in special modes 11.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. Module Base + 0x000B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 11-14.
PAGE 486
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.4 Functional Description 11.4.1 11.4.1.1 Functional Blocks Phase Locked Loop with Internal Filter (IPLL) The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 11-15 shows a block diagram of the IPLL.
PAGE 487
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-14. Examples of IPLL Divider Settings(1) fOSC REFDIV[5:0] fREF 4MHz $01 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz 8MHz $03 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz 4MHz $00 4MHz 01 $09 80MHz 01 $00 80MHz 40MHz 8MHz $00 8MHz 10 $04 80MHz 01 $00 80MHz 40MHz 4MHz $00 4MHz 01 $03 32MHz 00 $01 16MHz 8MHz 4MHz $01 2MHz 01 $18 100MHz 11 $01 1.
PAGE 488
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.4.1.2 System Clocks Generator PLLSEL or SCM PLLCLK PHASE LOCK LOOP (IIPLL) STOP 1 SYSCLK ÷2 SCM EXTAL 1 OSCILLATOR Core Clock 0 WAIT(RTIWAI), STOP(PSTP, PRE), RTI ENABLE CLOCK PHASE GENERATOR Bus Clock RTI OSCCLK 0 WAIT(COPWAI), STOP(PSTP, PCE), COP ENABLE XTAL COP Clock Monitor STOP Oscillator Clock Gating Condition = Clock Gate Figure 11-16.
PAGE 489
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.4.1.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.
PAGE 490
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) The Sequence for clock quality check is shown in Figure 11-18. CM FAIL CLOCK OK NO EXIT FULL STOP POR LVR YES SCME=1 & FSTWKP=1 ? NO NUM = 0 FSTWKP = 0 ? ENTER SCM YES CLOCK MONITOR RESET ENTER SCM NUM = 50 YES CHECK WINDOW SCM ACTIVE? NUM = NUM-1 YES OSC OK ? NUM = 0 NO NO NUM > 0 ? YES NO SCME = 1 ? NO YES SCM ACTIVE? YES SWITCH TO OSCCLK NO EXIT SCM Figure 11-18.
PAGE 491
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.4.1.5 Computer Operating Properly Watchdog (COP) The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 11.4.1.
PAGE 492
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) NOTE In order to detect a potential clock loss the CME bit should always be enabled (CME = 1). If CME bit is disabled and the MCU is configured to run on PLLCLK, a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards lower frequencies. As soon as the external clock is available again the system clock ramps up to its IPLL target frequency.
PAGE 493
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.4.3.3 Stop Mode All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or COP continues to run in Pseudo Stop Mode. In addition to disabling system and core clocks the S12XECRG requests other functional units of the MCU (e.g.
PAGE 494
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) CPU resumes program execution immediately Instruction STOP STOP FSTWKP=1 SCME=1 STOP Interrupt IRQ service IRQ service IRQ service Interrupt Interrupt Power Saving Oscillator Clock Oscillator Disabled PLL Clock Core Clock Self-Clock Mode Figure 11-19. Fast Wake-up from Full Stop Mode: Example 1 .
PAGE 495
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Table 11-16. Reset Summary 11.5.1 Reset Source Local Enable COP Watchdog Reset COPCTL (CR[2:0] nonzero) Description of Reset Operation The reset sequence is initiated by any of the following events: • Low level is detected at the RESET pin (External Reset). • Power on is detected. • Low voltage is detected. • Illegal Address Reset is detected (refer to device MMC information for details). • COP watchdog times out.
PAGE 496
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (External Reset), the internal reset remains asserted longer. Figure 11-21. RESET Timing RESET )( )( ICRG drives RESET pin low ) ) SYSCLK ( 128+n cycles possibly SYSCLK not running 11.5.1.
PAGE 497
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50 check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts using Self-Clock Mode.
PAGE 498
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) 11.6.1 11.6.1.1 Description of Interrupt Operation Real Time Interrupt The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1.
PAGE 499
Chapter 12 Pierce Oscillator (S12XOSCLCPV2) Table 12-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V01.05 19 Jul 2006 - All xclks info was removed V02.00 04 Aug 2006 - Incremented revision to match the design system spec revision 12.1 Introduction The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (1.
PAGE 500
Chapter 12 Pierce Oscillator (S12XOSCLCPV2) 12.1.3 Block Diagram Figure 12-1 shows a block diagram of the XOSC. Monitor_Failure Clock Monitor OSCCLK Peak Detector Gain Control VDDPLL = 1.8 V Rf XTAL EXTAL Figure 12-1. XOSC Block Diagram 12.2 External Signal Description This section lists and describes the signals that connect off chip 12.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry.
PAGE 501
Chapter 12 Pierce Oscillator (S12XOSCLCPV2) from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 12-2.
PAGE 502
Chapter 12 Pierce Oscillator (S12XOSCLCPV2) 12.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the oscillator module. 12.4 Functional Description The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. The oscillator block has two external pins, EXTAL and XTAL.
PAGE 503
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-1. Revision History Revision Number Revision Date V01.00 13 Oct. 2005 - Initial version V01.01 04 Mar. 2008 corrected reference to DJM bit 13.1 Sections Affected Description of Changes Introduction The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 13.1.
PAGE 504
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.1.2 13.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 13.1.2.2 • • • MCU Operating Modes Stop Mode — ICLKSTP=0 (in ATDCTL2 register) Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode.
PAGE 505
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.1.
PAGE 506
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.2 Signal Description This section lists all inputs to the ADC12B16C block. 13.2.1 Detailed Signal Descriptions 13.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger for the ATD conversion. 13.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 These inputs can be configured to serve as an external trigger for the ATD conversion.
PAGE 507
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Address Name 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDCMPEH 0x0009 ATDCMPEL 0x000A ATDSTAT2H 0x000B ATDSTAT2L 0x000C ATDDIENH 0x000D ATDDIENL 0x000E ATDCMPHTH 0x000F ATDCMPHTL 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATDDR7 0x0020 ATDDR8 0x0022 ATDDR9 R W R W R W R W R W R W R W R W R W R W R W R W
PAGE 508
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Address Name Bit 7 0x0024 ATDDR10 0x0026 ATDDR11 0x0028 ATDDR12 0x002A ATDDR13 0x002C ATDDR14 0x002E ATDDR15 6 5 4 3 2 1 See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” R W R W R W R W R W R W Bit 0 See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)” See Section 13.3.2.12.
PAGE 509
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-3. Multi-Channel Wrap Around Coding Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting WRAP3 WRAP2 WRAP1 WRAP0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 1. If only AN0 should be converted use MULT=0. 13.3.2.
PAGE 510
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-4. ATDCTL1 Field Descriptions (continued) Field Description 4 SMP_DIS Discharge Before Sampling Bit 0 No discharge before sampling. 1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to the sampling time. This can help to detect an open circuit instead of measuring the previous sampled channel.
PAGE 511
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.3.2.3 ATD Control Register 2 (ATDCTL2) Writes to this register will abort current conversion sequence. Module Base + 0x0002 7 R 6 5 4 3 2 1 0 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 13-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 13-7.
PAGE 512
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-7. ATDCTL2 Field Descriptions (continued) Field 1 ASCIE 0 ACMPIE Description ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set. ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE register) this bit enables the compare interrupt.
PAGE 513
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Field Description 6–3 S8C, S4C, S2C, S1C Conversion Sequence Length — These bits control the number of conversions per sequence. Table 13-11 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 family.
PAGE 514
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-11. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Table 13-12. ATD Behavior in Freeze Mode (Breakpoint) 13.3.2.
PAGE 515
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-13. ATDCTL4 Field Descriptions Field Description 7–5 SMP[2:0] Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). Table 13-14 lists the available sample time lengths. 4–0 PRS[4:0] ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS.
PAGE 516
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-15. ATDCTL5 Field Descriptions Field Description 6 SC Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD, CC, CB and CA of ATDCTL5. Table 13-16 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled 5 SCAN Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once.
PAGE 517
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-16. Analog Input Channel Select Coding SC CD CC CB CA Analog Input Channel 0 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 13.3.2.
PAGE 518
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Table 13-17. ATDSTAT0 Field Descriptions Field Description 7 SCF Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the flag is set after each one is completed.
PAGE 519
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Module Base + 0x0008 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CMPE[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 Figure 13-10. ATD Compare Enable Register (ATDCMPE) Table 13-18.
PAGE 520
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.3.2.9 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF[15:0]. Module Base + 0x000A 15 14 13 12 11 10 9 R 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CCF[15:0] W Reset 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-11. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime, no effect Table 13-19.
PAGE 521
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.3.2.10 ATD Input Enable Register (ATDDIEN) Module Base + 0x000C 15 14 13 12 11 10 9 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 IEN[15:0] W Reset 8 0 0 0 0 0 0 0 0 0 Figure 13-12. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 13-20.
PAGE 522
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.3.2.12 ATD Conversion Result Registers (ATDDRn) The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justification is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justified format depending on the actual value of the DJM bit.
PAGE 523
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Table 13-22. Conversion result mapping to ATDDRn A/D resolution 13.4 DJM conversion result mapping to ATDDRn 8-bit data 0 Bit[11:4] = result, Bit[3:0]=0000 8-bit data 1 Bit[7:0] = result, Bit[11:8]=0000 10-bit data 0 Bit[11:2] = result, Bit[1:0]=00 10-bit data 1 Bit[9:0] = result, Bit[11:10]=00 12-bit data X Bit[11:0] = result Functional Description The ADC12B16C is structured into an analog sub-block and a digital sub-block. 13.4.
PAGE 524
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output code. 13.4.2 Digital Sub-Block This subsection explains some of the digital features in more detail. See Section 13.3.2, “Register Descriptions” for all details. 13.4.2.
PAGE 525
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) 13.4.2.2 General-Purpose Digital Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled as analog channels to the A/D converter. The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog input channels of the ADC12B16C. The input pad signal is buffered to the digital port registers.
PAGE 526
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 527
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-1. Revision History Revision Number Revision Date V03.06 05 Aug 2009 V03.07 26 Aug 2009 14.3.2.2/14-536 - Add description, ?a counter overflow when TTOV[7] is set?, to be the 14.3.2.3/14-536 condition of channel 7 override event. 14.3.2.4/14-537 - Phrase the description of OC7M to make it more explicit V03.08 04 May 2010 14.3.2.8/14-540 - Add Table 14-11 14.3.2.11/14- - TCRE description, add Note and Figure 14-17 543 14.
PAGE 528
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) • • • Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-bit pulse accumulators. 16-bit modulus down-counter with 8-bit prescaler. Four user-selectable delay counters for input noise immunity increase. 14.1.2 • • • • Modes of Operation Stop — Timer and modulus counter are off since clocks are stopped.
PAGE 529
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.1.
PAGE 530
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.2.3 IOC5 — Input Capture and Output Compare Channel 5 This pin serves as input capture or output compare for channel 5. 14.2.4 IOC4 — Input Capture and Output Compare Channel 4 This pin serves as input capture or output compare for channel 4. 14.2.5 IOC3 — Input Capture and Output Compare Channel 3 This pin serves as input capture or output compare for channel 3. 14.2.
PAGE 531
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Register Name 0x0000 TIOS R W Bit 7 6 5 4 3 2 1 Bit 0 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0x0001 CFORC R 0 0 0 0 0 0 0 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0x0002 OC7M W OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0x0004 R TCNT (High) W TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0x0005 R TCNT (Low) W TCNT7 TCNT6 TCNT5 TC
PAGE 532
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Register Name Bit 7 0x000D TSCR2 W 0x000E TFLG1 W 0x000F TFLG2 R R R W TOI C7F TOF 6 5 4 3 2 1 Bit 0 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0x0010 R TC0 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0011 TC0 (Low) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0012 R TC1 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x0013 TC1 (L
PAGE 533
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x001C R TC6 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x001D TC6 (Low) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001E R TC7 (High) W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0x001F TC7 (Low) W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020 PACTL W PAEN PAMOD PEDGE CLK1 CLK0 PA0VI PAI 0 0 0 0 0 PA0VF PAIF 0x0021
PAGE 534
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Register Name 0x002B ICSYS W 0x002C OCPD W 0x002D TIMTST 0x002E PTPSR R R 0x0031 PBFLG 6 5 4 3 2 1 Bit 0 SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 R Timer Test Register W R W 0x002F R PTMCPSR W 0x0030 PBCTL Bit 7 R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 0 0 0 0 0 W PBOVI 0 0 0 0 0 0
PAGE 535
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x003A R TC1H (High) W TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0x003B R TC1H (Low) W TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0x003C R TC2H (High) W TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0x003D R TC2H (Low) W TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0x003E R TC3H (High) W TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0x003F R TC3H (Low) W TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 = Unimplemented or
PAGE 536
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.2 Timer Compare Force Register (CFORC) Module Base + 0x0001 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 Reset Figure 14-4. Timer Compare Force Register (CFORC) Read or write: Anytime but reads will always return 0x0000 (1 state is transient). All bits reset to zero. Table 14-3.
PAGE 537
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-4. OC7M Field Descriptions Field Description 7:0 OC7M[7:0] Output Compare Mask Action for Channel 7:0 A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,the output compare action reflects the corresponding OC7D bit.
PAGE 538
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Module Base + 0x0005 R W Reset 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 Figure 14-8. Timer Count Register Low (TCNT) Read: Anytime Write: Writable in special modes. All bits reset to zero. Table 14-6. TCNT Field Descriptions Field Description 15:0 Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value TCNT[15:0] of the counter.
PAGE 539
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-7. TSCR1 Field Descriptions (continued) Field Description 5 TSFRZ Timer and Modulus Counter Stop While in Freeze Mode 0 Allows the timer and modulus counter to continue running while in freeze mode. 1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. The pulse accumulators do not stop in freeze mode. 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally.
PAGE 540
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 R W Reset 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 Figure 14-11. Timer Control Register 1 (TCTL1) Module Base + 0x0009 R W Reset 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 Figure 14-12. Timer Control Register 2 (TCTL2) Read or write: Anytime All bits reset to zero.
PAGE 541
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-11.
PAGE 542
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-12. TCTL3/TCTL4 Field Descriptions Field Description EDG[7:0]B 7, 5, 3, 1 Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the active edge for the 16-bit pulse accumulator PACB.
PAGE 543
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R W Reset TOI 0 6 5 4 0 0 0 0 0 0 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 = Unimplemented or Reserved Figure 14-16. Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 544
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-15. TSCR2 Field Descriptions Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled. 1 Hardware interrupt requested when TOF flag set. Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output compare. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset disabled and counter free runs.
PAGE 545
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E R W Reset 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 Figure 14-18. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
PAGE 546
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG2 indicates when interrupt conditions have occurred.
PAGE 547
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Module Base + 0x0013 R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 14-23. Timer Input Capture/Output Compare Register 1 Low (TC1) Module Base + 0x0014 R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 14-24.
PAGE 548
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Module Base + 0x0019 R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 14-29. Timer Input Capture/Output Compare Register 4 Low (TC4) Module Base + 0x001A R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 14-30.
PAGE 549
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Module Base + 0x001F R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 14-35. Timer Input Capture/Output Compare Register 7 Low (TC7) Read: Anytime Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All bits reset to zero.
PAGE 550
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-19. PACTL Field Descriptions (continued) Field 4 PEDGE Description Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). Refer to Table 14-20. For PAMOD bit = 0 (event counter mode). 0 Falling edges on IC7 pin cause the count to be incremented 1 Rising edges on IC7 pin cause the count to be incremented For PAMOD bit = 1 (gated time accumulation mode).
PAGE 551
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.16 Pulse Accumulator A Flag Register (PAFLG) Module Base + 0x0021 R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PAOVF PAIF 0 0 = Unimplemented or Reserved Figure 14-37. Pulse Accumulator A Flag Register (PAFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
PAGE 552
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Module Base + 0x0023 R W Reset 7 6 5 4 3 2 1 0 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 0 0 0 0 0 0 0 0 Figure 14-39. Pulse Accumulators Count Register 2 (PACN2) Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator.
PAGE 553
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) All bits reset to zero. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set. Full count register access will take place in one clock cycle.
PAGE 554
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-23. MCCTL Field Descriptions (continued) Field Description 4 ICLAT Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers.
PAGE 555
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. Table 14-25. MCFLG Field Descriptions Field 7 MCZF 3:0 POLF[3:0] Description Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000. The flag indicates when interrupt conditions have occurred.
PAGE 556
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.22 Delay Counter Control Register (DLYCT) Module Base + 0x0029 R W Reset 7 6 5 4 3 2 1 0 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 0 0 0 0 0 0 0 0 Figure 14-45. Delay Counter Control Register (DLYCT) Read: Anytime Write: Anytime All bits reset to zero. Table 14-27.
PAGE 557
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-29. Delay Counter Select Examples when PRNT = 1 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 Delay 0 0 0 0 0 1 1 1 32 bus clock cycles 0 0 0 0 1 1 1 1 64 bus clock cycles 0 0 0 1 1 1 1 1 128 bus clock cycles 0 0 1 1 1 1 1 1 256 bus clock cycles 0 1 1 1 1 1 1 1 512 bus clock cycles 1 1 1 1 1 1 1 1 1024 bus clock cycles 14.3.2.
PAGE 558
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) All bits reset to zero. Table 14-31. ICSYS Field Descriptions Field Description 7:4 SHxy Share Input action of Input Capture Channels x and y 0 Normal operation 1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge detector is used to be active on the channel ‘y’.
PAGE 559
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.25 Output Compare Pin Disconnect Register (OCPD) Module Base + 0x002C R W Reset 7 6 5 4 3 2 1 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 0 0 0 0 Figure 14-48. Output Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 14-32. OCPD Field Descriptions Field Description 7:0 OCPD[7:0] Output Compare Pin Disconnect Bits 0 Enables the timer channel IO port.
PAGE 560
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-34.
PAGE 561
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-36.
PAGE 562
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Table 14-37. PBCTL Field Descriptions Field Description 6 PBEN Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR are set. 1 Pulse accumulator B system enabled.
PAGE 563
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.30 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H) Module Base + 0x0032 R 7 6 5 4 3 2 1 0 PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3H0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-53.
PAGE 564
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.31 Modulus Down-Counter Count Register (MCCNT) Module Base + 0x0036 R W Reset 15 14 13 12 11 10 9 8 MCCNT15 MCCNT14 MCCNT13 MCCNT12 MCCNT11 MCCNT10 MCCNT9 MCCNT8 1 1 1 1 1 1 1 1 Figure 14-57. Modulus Down-Counter Count Register High (MCCNT) Module Base + 0x0037 R W Reset 7 6 5 4 3 2 1 0 MCCNT7 MCCNT6 MCCNT5 MCCNT4 MCCNT3 MCCNT2 MCCNT1 MCCNT0 1 1 1 1 1 1 1 1 Figure 14-58.
PAGE 565
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.3.2.32 Timer Input Capture Holding Registers 0–3 (TCxH) Module Base + 0x0038 R 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-59. Timer Input Capture Holding Register 0 High (TC0H) Module Base + 0x0039 R 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-60.
PAGE 566
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Module Base + 0x003D R 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-64. Timer Input Capture Holding Register 2 Low (TC2H) Module Base + 0x003E R 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 14-65.
PAGE 567
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Bus Clock ÷ 1, 4, 8, 16 Bus Clock Timer Prescaler Modulus Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter 0 P0 Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. Pin Logic Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. PA2H Hold Reg.
PAGE 568
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Bus Clock ÷ 1, 2,3, ..., 256 Bus Clock Timer Prescaler Modulus Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter 0 P0 RESET Underflow 16-Bit Free-Running 16 BITMain MAINTimer TIMER ÷ 1, 2,3, ..., 256 Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 8, 12, 16, ..., 1024 0 P1 RESET Comparator Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg.
PAGE 569
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 16-Bit Free-Running 16 BITMain MAIN TIMER Timer ÷ 1, 4, 8, 16 Bus Clock 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. 0 P2 P4 Pin Logic Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. PA2H Hold Reg.
PAGE 570
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) ÷1, 2, 3, ... 256 Bus Clock 16-Bit Free-Running 16 BITMain MAIN TIMER Timer Timer Prescaler ÷ 1, 2, 3, ... 256 16-Bit Load Register Modulus Prescaler 16-Bit Modulus Down Counter Bus Clock 0 P0 RESET Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 LATCH0 8, 12, 16, ... 1024 RESET Comparator Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg.
PAGE 571
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) Load Holding Register and Reset Pulse Accumulator 0 8, 12,16, ..., 1024 8-Bit PAC0 (PACN0) EDG0 P0 Edge Detector Delay Counter PA0H Holding Register Interrupt 0 8, 12,16, ..., 1024 EDG1 P1 Edge Detector 8-Bit PAC1 (PACN1) Delay Counter PA1H Holding Register 0 8, 12,16, ..., 1024 EDG2 P2 Edge Detector 8-Bit PAC2 (PACN2) Delay Counter PA2H Holding Register Interrupt 8, 12,16, ...
PAGE 572
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) TIMCLK (Timer Clock) CLK1 CLK0 PACLK / 256 Clock Select (PAMOD) PACLK PACLK / 65536 Prescaled Clock (PCLK) 4:1 MUX Edge Detector P7 Interrupt 8-Bit PAC3 (PACN3) 8-Bit PAC2 (PACN2) MUX PACA Bus Clock Divide by 64 Interrupt 8-Bit PAC1 (PACN1) 8-Bit PAC0 (PACN0) Delay Counter PACB Edge Detector P0 Figure 14-72.
PAGE 573
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.4.1 Enhanced Capture Timer Modes of Operation The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called input capture (IC) channels.
PAGE 574
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 14.4.1.1, “IC Channels”). This will prevent the captured value from being overwritten until it is read or latched in the holding register. 2. IC Queue Mode (LATQ = 0) The main timer value is memorized in the IC register by a valid input pin transition (see Figure 1469 and Figure 14-70).
PAGE 575
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 4. Input pulses with a duration of DLY_CNT or longer are accepted. 14.4.1.2 OC Channel Initialization An internal compare channel whose output drives OCx may be programmed before the timer drives the output compare state (OCx).
PAGE 576
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) At the same time the pulse accumulator is cleared. 14.4.1.4 Modulus Down-Counter The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers. The action of latching can be programmed to be periodic or only once. 14.4.1.
PAGE 577
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.4.2 Reset The reset state of each individual bit is listed within the register description section (Section 14.3, “Memory Map and Register Definition”) which details the registers and their bit-fields. 14.4.3 Interrupts This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. Table 14-39 lists the interrupts generated by the ECT to communicate with the MCU. Table 14-39.
PAGE 578
Chapter 14 Enhanced Capture Timer (ECT16B8CV3) 14.4.3.5 Pulse Accumulator A Overflow Interrupt This active high output will be asserted by the module to request a timer pulse accumulator A overflow interrupt to be serviced by the system controller. 14.4.3.6 Timer Overflow Interrupt This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 579
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-1. Revision History Revision Number Sections Affected Revision Date Description of Changes V01.03 28 Jul 2006 15.7.1.7/15-601 - Update flow-chart of interrupt routine for 10-bit address V01.04 17 Nov 2006 15.3.1.2/15-582 - Revise Table1-5 V01.05 14 Aug 2007 15.3.1.1/15-581 - Backward compatible for IBAD bit name 15.
PAGE 580
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description • • General Call Address detection Compliant to ten-bit address 15.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 15.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 15-1. IIC Registers Start Stop Arbitration Control Clock Control In/Out Data Shift Register Interrupt bus_clock SCL SDA Address Compare Figure 15-1.
PAGE 581
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description 15.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers for the IIC module. 15.3.1 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
PAGE 582
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. Table 15-2. IBAD Field Descriptions Field Description 7:1 ADR[7:1] Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus.
PAGE 583
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-5. Prescale Divider Encoding IBC5-3 (bin) scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 000 2 7 4 1 001 2 7 4 2 010 2 9 6 4 011 6 9 6 8 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 Table 15-6.
PAGE 584
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description SDA SCL Hold(stop) SCL Hold(start) SCL START condition STOP condition Figure 15-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 15-7.
PAGE 585
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-7.
PAGE 586
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-7.
PAGE 587
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-7.
PAGE 588
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-7.
PAGE 589
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-7. IIC Divider and Hold Values (Sheet 6 of 6) IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop) 15.3.1.
PAGE 590
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-8. IBCR Field Descriptions Field Description 7 IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.
PAGE 591
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively. 15.3.1.
PAGE 592
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description Table 15-9. IBSR Field Descriptions (continued) Field Description 2 SRW Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated.
PAGE 593
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description 15.3.1.6 IIC Control Register 2(IBCR2) Module Base + 0x0005 7 6 GCEN ADTYPE 0 0 R 5 4 3 0 0 0 2 1 0 ADR10 ADR9 ADR8 0 0 0 W Reset 0 0 0 Figure 15-9. IIC Bus Control Register 2(IBCR2) This register contains the variables used in general call and in ten-bit address. Read and write anytime Table 15-10. IBCR2 Field Descriptions Field Description General Call Enable. 0 General call is disabled.
PAGE 594
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description MSB CL 1 DA LSB 2 3 4 5 6 7 8 MSB 9 ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W Start Signal Calling Address Read/ Write MSB CL 1 DA XXX 3 4 5 6 7 8 Calling Address Read/ Write 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 1 XX Ack Bit 9 No Ack Bit MSB 9 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W Start Signal 2 Ack Bit LSB 2 LSB 1 LSB 3 2 4 5 6 7 8 9 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W Repeat
PAGE 595
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description 15.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave.
PAGE 596
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description 15.4.1.5 Repeated START Signal As shown in Figure 15-10, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 15.4.1.
PAGE 597
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description 15.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 15.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer.
PAGE 598
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the address match. In order to distinguish whether the address match is the normal address match or the general call address match, IBDR should be read after the address byte has been received. If the data is $00, the match is general call address match.
PAGE 599
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine. 15.7 Application Information 15.7.1 15.7.1.1 IIC Programming Examples Initialization Sequence Reset will put the IIC bus control register to its default status.
PAGE 600
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description IBFREE 15.7.1.3 MOVB CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS, D0=R/W BRCLR IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET Post-Transfer Software Response Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished.
PAGE 601
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver. MASR DEC BEQ MOVB DEC BNE BSET RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 ENMASR NXMAR BRA BCLR MOVB RTI NXMAR IBCR,#$20 IBDR,RXBUF 15.7.1.
PAGE 602
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set.
PAGE 603
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description CAUTION When IIC is configured as 10-bit address,the point of the data array in interrupt routine must be reset after it’s addressed. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 604
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description MC9S12XE-Family Reference Manual Rev. 1.
PAGE 605
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-1. Revision History Revision Number Revision Date V03.13 03 Mar 2011 Figure 16-4 Table 16-3 • Corrected CANE write restrictions • Removed footnote from RXFRM bit V03.14 12 Nov 2012 Table 16-11 • Corrected RxWRN and TxWRN threshold values V03.15 12 Jan 2013 Table 16-3 Table 16-26 Figure 16-37 16.1/16-605 16.3.2.15/16626 16.
PAGE 606
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.1.1 Glossary Table 16-2. Terminology ACK Acknowledge of CAN message CAN Controller Area Network CRC Cyclic Redundancy Code EOF End of Frame FIFO First-In-First-Out Memory IFS Inter-Frame Sequence SOF Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock 16.1.
PAGE 607
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.
PAGE 608
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.2 External Signal Description The MSCAN uses two external pins. NOTE On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional. 16.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 16.2.
PAGE 609
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 16.3.1 Module Memory Map Figure 16-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description.
PAGE 610
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x0000 CANCTL0 0x0001 CANCTL1 Bit 7 R W R W 0x0002 CANBTR0 R 0x0003 CANBTR1 R 0x0004 CANRFLG R 0x0005 CANRIER R 0x0006 CANTFLG 0x0007 CANTIER W W W W R R 0x0009 CANTAAK W R R R SYNCH 3 2 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WUPIF CSCIF
PAGE 611
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x000F CANTXERR R 0x0010–0x0013 CANIDAR0–3 R 0x0014–0x0017 CANIDMRx R 0x0018–0x001B CANIDAR4–7 R 0x001C–0x001F CANIDMR4–7 R 0x0020–0x002F CANRXFG R 0x0030–0x003F CANTXFG R Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 A
PAGE 612
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).
PAGE 613
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-3. CANCTL0 Register Field Descriptions (continued) Field Description 1 SLPRQ(4) Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 16.4.5.5, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty.
PAGE 614
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x0001 7 6 5 4 3 2 CANE CLKSRC LOOPB LISTEN BORM WUPM 0 0 0 1 0 0 R 1 0 SLPAK INITAK 0 1 W Reset: = Unimplemented Figure 16-5. MSCAN Control Register 1 (CANCTL1) 1.
PAGE 615
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-4. CANCTL1 Register Field Descriptions (continued) Field Description 1 SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 16.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
PAGE 616
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-7. Baud Rate Prescaler 16.3.2.4 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
PAGE 617
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-9. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle(1) 0 0 1 2 Tq clock cycles : : : : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles 1. This setting is not valid. Please refer to Table 16-37 for valid settings. Table 16-10.
PAGE 618
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Table 16-11.
PAGE 619
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-11. CANRFLG Register Field Descriptions (continued) Field Description 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected 0 RXF(2) Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
PAGE 620
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-12. CANRIER Register Field Descriptions Field 7 WUPIE(1) 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
PAGE 621
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x0006 R 7 6 5 4 3 0 0 0 0 0 2 1 0 TXE2 TXE1 TXE0 1 1 1 W Reset: 0 0 0 0 0 = Unimplemented Figure 16-10. MSCAN Transmitter Flag Register (CANTFLG) 1.
PAGE 622
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime when not in initialization mode NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 16-14. CANTIER Register Field Descriptions Field Description 2-0 TXEIE[2:0] 16.3.2.
PAGE 623
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. Access: User read/write(1) Module Base + 0x0009 R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 16-13.
PAGE 624
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Table 16-17. CANTBSEL Register Field Descriptions Field Description 2-0 TX[2:0] Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g.
PAGE 625
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-18. CANIDAC Register Field Descriptions Field Description 5-4 IDAM[1:0] Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 16.4.3, “Identifier Acceptance Filter”). Table 16-19 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded.
PAGE 626
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x000C R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 16-16. MSCAN Reserved Register 1. Read: Always reads zero in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special system operating modes can alter the MSCAN functionality. 16.3.2.
PAGE 627
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x000E R 7 6 5 4 3 2 1 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 16-18. MSCAN Receive Error Counter (CANRXERR) 1.
PAGE 628
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 16.3.
PAGE 629
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-23. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7-0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. 16.3.2.
PAGE 630
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1. Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 16-25. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description 7-0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match.
PAGE 631
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-26.
PAGE 632
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 16-24.
PAGE 633
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 16-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued) Register Name Bit 7 6 5 4 3 2 1 Bit0 = Unused, always read ‘x’ Read: • For transmit buffers, anytime when TXEx flag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
PAGE 634
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 x x x x x x x x R W Reset: Figure 16-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping Table 16-27.
PAGE 635
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 7 6 5 4 3 2 1 0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 x x x x x x x x R W Reset: Figure 16-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 16-29. IDR2 Register Field Descriptions — Extended Field Description 7-0 ID[14:7] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
PAGE 636
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping Module Base + 0x00X0 7 6 5 4 3 2 1 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 x x x x x x x x R W Reset: Figure 16-30. Identifier Register 0 — Standard Mapping Table 16-31. IDR0 Register Field Descriptions — Standard Field Description 7-0 ID[10:3] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format.
PAGE 637
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x00X2 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 16-32. Identifier Register 2 — Standard Mapping Module Base + 0x00X3 7 6 5 4 3 2 1 0 x x x x x x x x R W Reset: = Unused; always read ‘x’ Figure 16-33. Identifier Register 3 — Standard Mapping 16.3.3.
PAGE 638
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. Module Base + 0x00XC 7 6 5 4 3 2 1 0 DLC3 DLC2 DLC1 DLC0 x x x x R W Reset: x x x x = Unused; always read “x” Figure 16-35. Data Length Register (DLR) — Extended Identifier Mapping Table 16-34.
PAGE 639
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) • The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. Access: User read/write(1) Module Base + 0x00XD 7 6 5 4 3 2 1 0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 0 0 0 0 0 0 0 0 R W Reset: Figure 16-36. Transmit Buffer Priority Register (TBPR) 1.
PAGE 640
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Access: User read/write(1) Module Base + 0x00XF R 7 6 5 4 3 2 1 0 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 x x x x x x x x W Reset: Figure 16-38. Time Stamp Register — Low Byte (TSRL) 1. Read: or transmit buffers: Anytime when TXEx flag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.
PAGE 641
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.4 16.4.1 Functional Description General This section provides a complete functional description of the MSCAN. 16.4.2 Message Storage CAN Receive / Transmit Engine Memory Mapped I/O Rx0 RXF CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 Receiver TxBG Tx0 MSCAN TxFG Tx1 Transmitter TxBG Tx2 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 16-39.
PAGE 642
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 16.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages.
PAGE 643
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
PAGE 644
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) generates a receive interrupt1 (see Section 16.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS field of the CAN frame, is received into the next available RxBG.
PAGE 645
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Figure 16-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. Four identifier acceptance filters, each to be applied to: — The 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages.
PAGE 646
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 16-41.
PAGE 647
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
PAGE 648
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
PAGE 649
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn.
PAGE 650
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-36. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
PAGE 651
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.4.4.2 Special System Operating Modes The MSCAN module behaves as described within this specification in all special system operating modes. Write restrictions which exist on specific registers in normal modes are lifted for test purposes in special modes. 16.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like in normal system operating modes as described within this specification. 16.4.4.
PAGE 652
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Bus Clock Domain CAN Clock Domain INITRQ SYNC sync. INITRQ sync. SYNC INITAK CPU Init Request INITAK Flag INITAK INIT Flag Figure 16-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Figure 16-45).
PAGE 653
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 16-38. CPU vs. MSCAN Operating Modes MSCAN Mode Reduced Power Consumption CPU Mode Normal Sleep RUN CSWAI = X(1) SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 WAIT CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 1 SLPAK = 1 STOP Power Down Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X 1.
PAGE 654
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.4.5.5 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register.
PAGE 655
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect.
PAGE 656
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.4.5.7 Disabled Mode The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as specified. 16.4.5.8 Programmable Wake-Up Function The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0).
PAGE 657
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer. 16.4.7.
PAGE 658
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) 16.5 16.5.1 Initialization/Application Information MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode If the configuration of registers which are only writable in initialization mode shall be changed: 1.
PAGE 659
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Table 17-1. Revision History Revision Number RevisionDate V01.00 28 Apr 2005 V01.01 05 Jul 2005 17.1 Sections Affected Description of Changes - Initial Release. 17.6/17-674 - Added application section. - Removed table 1-1. Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 17-1 for a simplified block diagram. 17.1.
PAGE 660
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) • Run mode This is the basic mode of operation. Wait mode PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register. In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled. Stop mode In full stop mode or pseudo stop mode, the PIT module is stalled.
PAGE 661
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) 17.3 Register Definition This section consists of register descriptions in address order of the PIT. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
PAGE 662
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x000E R PITCNT1 (High) W PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 R 0x000F PITCNT1 (Low) W PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0x0010 PITLD2 (High) W PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 0x0011 PITLD2 (Low) W PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x0012 R PITCNT2 (High) W PCNT15 PCNT14
PAGE 663
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x001E R PITCNT5 (High) W PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 0x001F R PITCNT5 (Low) W PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0x0020 PITLD6 (High) PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x0022 R PITCNT
PAGE 664
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) 17.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT) Module Base + 0x0000 7 R W Reset 6 5 PITE PITSWAI PITFRZ 0 0 0 4 3 2 1 0 0 0 0 0 0 PFLMT1 PFLMT0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 17-2.
PAGE 665
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Table 17-3. PITFLT Field Descriptions Field Description 7:0 PFLT[7:0] PIT Force Load Bits for Timer 7-0 — These bits have only an effect if the corresponding timer channel (PCE set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding 16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will always return zero. 17.3.0.
PAGE 666
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Table 17-5. PITMUX Field Descriptions Field Description 7:0 PMUX[7:0] PIT Multiplex Bits for Timer Channel 7:0 — These bits select if the corresponding 16-bit timer is connected to micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is immediately switched to the other micro time base. 0 The corresponding 16-bit timer counts with micro time base 0. 1 The corresponding 16-bit timer counts with micro time base 1. 17.3.0.
PAGE 667
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Table 17-7. PITTF Field Descriptions Field Description 7:0 PTF[7:0] PIT Time-out Flag Bits for Timer Channel 7:0 — PTF is set when the corresponding 16-bit timer modulus down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. The flag can be cleared by writing a one to the flag bit. Writing a zero has no effect.
PAGE 668
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Module Base + 0x000C, 0x000D 15 R W Reset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 17-12.
PAGE 669
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Module Base + 0x0024, 0x0025 15 R W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17-18. PIT Load Register 7 (PITLD7) Read: Anytime Write: Anytime Table 17-9. PITLD0–7 Field Descriptions Field Description 15:0 PLD[15:0] PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value.
PAGE 670
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Module Base + 0x0016, 0x0017 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT PCNT PCNT PCNT PCNT PCNT PCN PCN PCN PCN PCN PCN PCN PCN PCN PCN 15 14 13 12 11 10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 17-22.
PAGE 671
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) 17.4 Functional Description Figure 17-27 shows a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, eight 16-bit down-counters and an interrupt/trigger interface.
PAGE 672
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) 17.4.1 Timer As shown in Figure 17-1 and Figure 17-27, the 24-bit timers are built in a two-stage architecture with eight 16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer is connected to micro time base 0 or 1 via the PMUX[7:0] bit setting in the PIT Multiplex (PITMUX) register.
PAGE 673
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) Bus Clock 8-Bit Micro 0 Timer Counter PITCNT Register 00 2 1 0 2 0001 1 0 2 0000 1 0001 0 2 1 0000 2 1 0 0001 2 1 0 2 0000 1 0 2 0001 8-Bit Force Load 16-Bit Force Load PTF Flag1 PITTRIG Time-Out Period Note 1. The PTF flag clearing depends on the software Time-Out Period After Restart Figure 17-28. PIT Trigger and Flag Signal Timing 17.4.
PAGE 674
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) 17.5 17.5.1 Initialization Startup Set the configuration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the configuration registers can be written in arbitrary order. 17.5.2 Shutdown When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are cleared, the corresponding PIT interrupt flags are cleared.
PAGE 675
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) MOVB MOVB CLI #$01,PITINTE #$80,PITCFLMT ; enable interupt channel 0 ; enable PIT ; clear Interupt disable Mask bit ;******************** Main Program ************************************************************* MAIN: BRA * ; loop until interrupt ;******************** Channel 0 Interupt Routine *************************************************** CH0_ISR: LDAA MOVB RTI PITTF #$01,PITTF ; 8 bit read of PIT time out flags ; clear PIT channel 0 time
PAGE 676
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 677
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Table 18-1. Revision History Revision Number Revision Date V01.00 28 Apr 2005 V01.01 05 Jul 2005 18.1 Sections Affected Description of Changes - Initial Release 18.6/18-690 - Added application section. - Removed table 1-1 Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 18-1 for a simplified block diagram. 18.1.
PAGE 678
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) • Run mode This is the basic mode of operation. Wait mode PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register. In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled. Stop mode In full stop mode or pseudo stop mode, the PIT module is stalled.
PAGE 679
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Register Name 0x0000 PITCFLMT R W 0x0001 PITFLT W 0x0002 PITCE W Bit 7 6 5 PITE PITSWAI PITFRZ 0 0 0 R 3 2 1 Bit 0 0 0 0 0 0 PFLMT1 PFLMT0 0 0 0 0 0 PFLT3 PFLT2 PFLT1 PFLT0 PCE3 PCE2 PCE1 PCE0 PMUX3 PMUX2 PMUX1 PMUX0 PINTE3 PINTE2 PINTE1 PINTE0 PTF3 PTF2 PTF1 PTF0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 PMTLD7 PMTLD6 PMTLD5 PMTLD4
PAGE 680
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000F R PITCNT1 (Low) W PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0x0010 PITLD2 (High) PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 0x0012 R PITCNT2 (High) W PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 0x0013 R PITCNT2 (Low) W PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0x0014 PITLD3 (High) PLD15 PLD14
PAGE 681
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Table 18-2. PITCFLMT Field Descriptions Field Description 7 PITE PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and flag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start downcounting with the corresponding load register values. 0 PIT disabled (lower power consumption). 1 PIT is enabled.
PAGE 682
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) 18.3.0.3 PIT Channel Enable Register (PITCE) Module Base + 0x0002 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PCE3 PCE2 PCE1 PCE0 0 0 0 0 Figure 18-5. PIT Channel Enable Register (PITCE) Read: Anytime Write: Anytime Table 18-4. PITCE Field Descriptions Field Description 3:0 PCE[3:0] PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0.
PAGE 683
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) 18.3.0.4 PIT Multiplex Register (PITMUX) Module Base + 0x0003 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PMUX3 PMUX2 PMUX1 PMUX0 0 0 0 0 Figure 18-6. PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime Table 18-5. PITMUX Field Descriptions Field Description 3:0 PMUX[3:0] PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to micro time base 1 or 0.
PAGE 684
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) 18.3.0.6 PIT Time-Out Flag Register (PITTF) Module Base + 0x0005 R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PTF3 PTF2 PTF1 PTF0 0 0 0 0 Figure 18-8. PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear) Table 18-7.
PAGE 685
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Table 18-8. PITMTLD0–1 Field Descriptions Field Description 7:0 PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers. PMTLD[7:0] Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down to zero, the PMTLD register value will be loaded.
PAGE 686
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Table 18-9. PITLD0–3 Field Descriptions Field Description 15:0 PLD[15:0] PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer has counted down to zero the PTF time-out flag will be set and the register value will be loaded.
PAGE 687
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Table 18-10. PITCNT0–3 Field Descriptions Field Description 15:0 PIT Count Bits 15-0 — These bits represent the current 16-bit modulus down-counter value. The read access PCNT[15:0] for the count register must take place in one clock cycle as a 16-bit access. 18.4 Functional Description Figure 18-19 shows a detailed block diagram of the PIT module.
PAGE 688
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the connected 16-bit modulus down-counters count one cycle. Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set, as shown in Figure 18-20.
PAGE 689
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) 18.4.2 Interrupt Interface Each time-out event can be used to trigger an interrupt service request. For each timer channel, an individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit.
PAGE 690
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) modify-write instruction which writes back the “bit-wise or” of the flag_register and the mask into the flag_register. BSET would clear all flag bits that were set, independent from the mask. For example, to clear flag bit 0 use: MOVB #$01,PITTF. 18.6 Application Information To get started quickly with the PIT24B4C module this section provides a small code example how to use the block.
PAGE 691
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Table 19-1. Revision History Revision Number Revision Date Sections Affected 1.1 28 Sepr 2012 1.4.2.6 19.1 Description of Changes deleted the blank in the doc Introduction The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.
PAGE 692
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. 19.1.3 Block Diagram Figure 19-1 shows the block diagram for the 8-bit 8-channel PWM block.
PAGE 693
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.2.2 PWM6 — PWM Channel 6 This pin serves as waveform output of PWM channel 6. 19.2.3 PWM5 — PWM Channel 5 This pin serves as waveform output of PWM channel 5. 19.2.4 PWM4 — PWM Channel 4 This pin serves as waveform output of PWM channel 4. 19.2.5 PWM3 — PWM Channel 3 This pin serves as waveform output of PWM channel 3. 19.2.6 PWM3 — PWM Channel 2 This pin serves as waveform output of PWM channel 2. 19.2.
PAGE 694
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 19.3.2 Register Descriptions This section describes in detail all the registers and register bits in the PWM module.
PAGE 695
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 R 0x000B PWMSCNTB W 1 0 0 0 0 0 0 0 0 0x000C R PWMCNT0 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000D R PWMCNT1 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000E R PWMCNT2 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x000F R PWMCNT3 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0x0010 R PWMCNT4 W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0
PAGE 696
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x001A R PWMPER6 W Bit 7 6 5 4 3 2 1 Bit 0 0x001B R PWMPER7 W Bit 7 6 5 4 3 2 1 Bit 0 0x001C R PWMDTY0 W Bit 7 6 5 4 3 2 1 Bit 0 0x001D R PWMDTY1 W Bit 7 6 5 4 3 2 1 Bit 0 0x001E R PWMDTY2 W Bit 7 6 5 4 3 2 1 Bit 0 0x001F R PWMDTY3 W Bit 7 6 5 4 3 2 1 Bit 0 0x0020 R PWMDTY4 W Bit 7 6 5 4 3 2 1 Bit 0 0x0021 R PWMDTY5 W Bit 7 6 5 4 3 2 1 Bit 0
PAGE 697
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts off for power savings.
PAGE 698
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Table 19-2. PWME Field Descriptions (continued) Field Description 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled.
PAGE 699
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 0 0 0 0 0 0 0 0 Figure 19-5. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 19-4.
PAGE 700
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x0003 7 R 0 W Reset 0 6 5 4 3 PCKB2 PCKB1 PCKB0 0 0 0 0 2 1 0 PCKA2 PCKA1 PCKA0 0 0 0 0 = Unimplemented or Reserved Figure 19-6. PWM Prescale Clock Select Register (PWMPRCLK) Read: Anytime Write: Anytime NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 19-5.
PAGE 701
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See Section 19.4.2.5, “Left Aligned Outputs” and Section 19.4.2.
PAGE 702
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 19.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. Table 19-9.
PAGE 703
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. Module Base + 0x0006 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 19-9.
PAGE 704
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Module Base + 0x0008 R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 19-11. PWM Scale A Register (PWMSCLA) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value) 19.3.2.
PAGE 705
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Module Base + 0x000A, 0x000B R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 19-13. Reserved Registers (PWMSCNTx) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality. 19.3.2.
PAGE 706
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime (any value written causes PWM counter to be reset to $00). 19.3.2.13 PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel.
PAGE 707
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state.
PAGE 708
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Write: Anytime 19.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. Module Base + 0x0024 R W Reset 7 6 PWMIF PWMIE 0 0 5 0 PWMRSTRT 0 4 PWMLVL 0 3 2 0 PWM7IN 0 0 1 0 PWM7INL PWM7ENA 0 0 = Unimplemented or Reserved Figure 19-17.
PAGE 709
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.4 Functional Description 19.4.1 PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter.
PAGE 710
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Clock A PCKA2 PCKA1 PCKA0 Clock A/2, A/4, A/6,....A/512 8-Bit Down Counter M U X Load DIV 2 Clock to PWM Ch 0 PCLK0 Count = 1 PWMSCLA M U X Clock SA PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 M U X 2 4 8 16 32 64 128 Divide by Prescaler Taps: X PCLK3 Clock B Clock B/2, B/4, B/6,....
PAGE 711
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register.
PAGE 712
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period.
PAGE 713
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 19.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal.
PAGE 714
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops.
PAGE 715
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 19-20.
PAGE 716
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 19-21. PWM Left Aligned Output Example Waveform 19.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00.
PAGE 717
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
PAGE 718
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits.
PAGE 719
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Clock Source 7 High Low PWMCNT6 PWCNT7 Period/Duty Compare PWM7 Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 19-24.
PAGE 720
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 19-12 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 19-12. 16-bit Concatenation Mode Summary 19.4.2.
PAGE 721
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) 19.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active.
PAGE 722
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 723
Chapter 20 Serial Communication Interface (S12SCIV5) Table 20-1. Revision History Version Revision Effective Number Date Date 05.03 12/25/2008 Author Description of Changes 05.04 08/05/2009 remove redundancy comments in Figure1-2 fix typo, SCIBDL reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, Table 20-4,SCICR1 Even parity should be PT=0 fix typo, on page 20-745,should be BKDIF,not BLDIF 20.
PAGE 724
Chapter 20 Serial Communication Interface (S12SCIV5) 20.1.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.
PAGE 725
Chapter 20 Serial Communication Interface (S12SCIV5) 20.1.4 Block Diagram Figure 20-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
PAGE 726
Chapter 20 Serial Communication Interface (S12SCIV5) 20.2 External Signal Description The SCI module has a total of two external pins. 20.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 20.2.2 RXD — Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high.
PAGE 727
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
PAGE 728
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) Module Base + 0x0000 R W Reset 7 6 5 4 3 2 1 0 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 Figure 20-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 R W Reset 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 Figure 20-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0.
PAGE 729
Chapter 20 Serial Communication Interface (S12SCIV5) Table 20-3. IRSCI Transmit Pulse Width 20.3.2.2 TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 SCI Control Register 1 (SCICR1) Module Base + 0x0002 R W Reset 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Figure 20-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0.
PAGE 730
Chapter 20 Serial Communication Interface (S12SCIV5) Table 20-4. SCICR1 Field Descriptions (continued) Field Description 2 ILT Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character.
PAGE 731
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.3 SCI Alternative Status Register 1 (SCIASR1) Module Base + 0x0000 7 R W Reset RXEDGIF 0 6 5 4 3 2 0 0 0 0 BERRV 0 0 0 0 0 1 0 BERRIF BKDIF 0 0 = Unimplemented or Reserved Figure 20-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 20-6.
PAGE 732
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.4 SCI Alternative Control Register 1 (SCIACR1) Module Base + 0x0001 7 R W Reset RXEDGIE 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 BERRIE BKDIE 0 0 = Unimplemented or Reserved Figure 20-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 20-7.
PAGE 733
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.5 SCI Alternative Control Register 2 (SCIACR2) Module Base + 0x0002 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 BERRM1 BERRM0 BKDFE 0 0 0 = Unimplemented or Reserved Figure 20-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 20-8.
PAGE 734
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.6 SCI Control Register 2 (SCICR2) Module Base + 0x0003 R W Reset 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 20-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 20-10. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
PAGE 735
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.
PAGE 736
Chapter 20 Serial Communication Interface (S12SCIV5) Table 20-11. SCISR1 Field Descriptions (continued) Field Description 3 OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
PAGE 737
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.8 SCI Status Register 2 (SCISR2) Module Base + 0x0005 7 R W Reset AMAP 0 6 5 0 0 0 0 4 3 2 1 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 RAF 0 = Unimplemented or Reserved Figure 20-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 20-12. SCISR2 Field Descriptions Field Description 7 AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible.
PAGE 738
Chapter 20 Serial Communication Interface (S12SCIV5) 20.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) Module Base + 0x0006 7 R 6 R8 W Reset 0 T8 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 20-13.
PAGE 739
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 20-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
PAGE 740
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s.
PAGE 741
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 20-15 below.
PAGE 742
Chapter 20 Serial Communication Interface (S12SCIV5) 1. The address bit identifies the frame as an address character. See Section 20.4.6.6, “Receiver Wakeup”. 20.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL).
PAGE 743
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.
PAGE 744
Chapter 20 Serial Communication Interface (S12SCIV5) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate.
PAGE 745
Chapter 20 Serial Communication Interface (S12SCIV5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out.
PAGE 746
Chapter 20 Serial Communication Interface (S12SCIV5) Figure 20-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission.
PAGE 747
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 20-18.
PAGE 748
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.
PAGE 749
Chapter 20 Serial Communication Interface (S12SCIV5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 20.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
PAGE 750
Chapter 20 Serial Communication Interface (S12SCIV5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 20-18 summarizes the results of the data bit samples. Table 20-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
PAGE 751
Chapter 20 Serial Communication Interface (S12SCIV5) In Figure 20-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
PAGE 752
Chapter 20 Serial Communication Interface (S12SCIV5) In Figure 20-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
PAGE 753
Chapter 20 Serial Communication Interface (S12SCIV5) Figure 20-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
PAGE 754
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values.
PAGE 755
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.6.5.2 Fast Data Tolerance Figure 20-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 20-29.
PAGE 756
Chapter 20 Serial Communication Interface (S12SCIV5) 20.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state.
PAGE 757
Chapter 20 Serial Communication Interface (S12SCIV5) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
PAGE 758
Chapter 20 Serial Communication Interface (S12SCIV5) 20.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE.
PAGE 759
Chapter 20 Serial Communication Interface (S12SCIV5) 20.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 20.
PAGE 760
Chapter 20 Serial Communication Interface (S12SCIV5) 20.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 20.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected.
PAGE 761
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-1. Revision History Revision Number Revision Date Sections Affected V05.00 24 Mar 2005 21.3.2/21-765 21.1 Description of Changes - Added 16-bit transfer width feature. Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 21.1.1 Glossary of Terms SPI SS SCK MOSI MISO MOMI SISO 21.1.
PAGE 762
Chapter 21 Serial Peripheral Interface (S12SPIV5) • • • Run mode This is the basic mode of operation. Wait mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off.
PAGE 763
Chapter 21 Serial Peripheral Interface (S12SPIV5) SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register SPIF MODF SPTEF Interrupt Control SPI Interrupt Request Baud Rate Generator Slave Control CPOL CPHA Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Master Control Counter Bus Clock Prescaler Clock Select SPPR 3 SPR MOSI Port Control Logic SCK SS Baud Rate Shift Clock Sample Clock 3 Shifter SPI Baud Rate Reg
PAGE 764
Chapter 21 Serial Peripheral Interface (S12SPIV5) 21.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave. 21.2.4 SCK — Serial Clock Pin In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock. 21.
PAGE 765
Chapter 21 Serial Peripheral Interface (S12SPIV5) 21.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. 21.3.2.1 SPI Control Register 1 (SPICR1) Module Base +0x0000 R W Reset 7 6 5 4 3 2 1 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 0 0 1 0 0 Figure 21-3.
PAGE 766
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-2. SPICR1 Field Descriptions (continued) Field Description 1 SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 21-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 LSBFE LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register.
PAGE 767
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-4. SPICR2 Field Descriptions Field Description 6 XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Please refer to Section 21.3.2.
PAGE 768
Chapter 21 Serial Peripheral Interface (S12SPIV5) 21.3.2.3 SPI Baud Rate Register (SPIBR) Module Base +0x0002 7 R 6 0 W Reset 0 5 4 3 SPPR2 SPPR1 SPPR0 0 0 0 0 2 1 0 SPR2 SPR1 SPR0 0 0 0 0 = Unimplemented or Reserved Figure 21-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 21-6.
PAGE 769
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 2 of 3) Baud Rate Divisor Baud Rate 0 64 390.63 kbit/s 1 128 195.31 kbit/s 1 0 256 97.66 kbit/s 1 1 512 48.83 kbit/s 0 0 0 6 4.16667 Mbit/s 0 0 1 12 2.08333 Mbit/s 0 0 1 0 24 1.04167 Mbit/s 0 0 1 1 48 520.83 kbit/s 1 0 1 0 0 96 260.42 kbit/s 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.
PAGE 770
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3) Baud Rate Divisor Baud Rate 0 896 27.90 kbit/s 1 1792 13.95 kbit/s 0 0 16 1.5625 Mbit/s 0 1 32 781.25 kbit/s 0 1 0 64 390.63 kbit/s 0 1 1 128 195.31 kbit/s 1 1 0 0 256 97.66 kbit/s 1 1 0 1 512 48.83 kbit/s 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 2048 12.
PAGE 771
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-9. SPIF Interrupt Flag Clearing Sequence XFRW Bit SPIF Interrupt Flag Clearing Sequence 0 Read SPISR with SPIF == 1 1 Read SPISR with SPIF == 1 then Read SPIDRL Byte Read SPIDRL (1) or then Byte Read SPIDRH (2) Byte Read SPIDRL or Word Read (SPIDRH:SPIDRL) 1. Data in SPIDRH is lost in this case. 2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF == 1.
PAGE 772
Chapter 21 Serial Peripheral Interface (S12SPIV5) 21.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL) Module Base +0x0004 7 6 5 4 3 2 1 0 R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 0 0 0 0 0 0 0 0 Reset Figure 21-7. SPI Data Register High (SPIDRH) Module Base +0x0005 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 21-8.
PAGE 773
Chapter 21 Serial Peripheral Interface (S12SPIV5) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data B Data A = Unspecified Data C = Reception in progress Figure 21-9.
PAGE 774
Chapter 21 Serial Peripheral Interface (S12SPIV5) The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1 register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions by the S-clock from the master, so data is exchanged between the master and the slave.
PAGE 775
Chapter 21 Serial Peripheral Interface (S12SPIV5) drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state.
PAGE 776
Chapter 21 Serial Peripheral Interface (S12SPIV5) As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched.
PAGE 777
Chapter 21 Serial Peripheral Interface (S12SPIV5) The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device.
PAGE 778
Chapter 21 Serial Peripheral Interface (S12SPIV5) End of Idle State Begin 1 SCK Edge Number 2 3 4 5 6 7 8 Begin of Idle State End Transfer 9 10 11 12 13 14 15 16 Bit 1 Bit 6 LSB Minimum 1/2 SCK for tT, tl, tL MSB SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL =
PAGE 779
Chapter 21 Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) MSB first (LSBFE = 0) LSB first (LSBFE = 1) tL tT tI tL MSB Bit 14Bit 13Bit 12Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit
PAGE 780
Chapter 21 Serial Peripheral Interface (S12SPIV5) When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave.
PAGE 781
Chapter 21 Serial Peripheral Interface (S12SPIV5) End of Idle State SCK Edge Number Begin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Begin of Idle State End Transfer 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tI tL Minimum 1/2 SCK for tT, tl, tL tL MSB first (LSBFE = 0) LSB first (LSBFE = 1) MSB Bit 14Bit 13Bit 12Bit
PAGE 782
Chapter 21 Serial Peripheral Interface (S12SPIV5) When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2.
PAGE 783
Chapter 21 Serial Peripheral Interface (S12SPIV5) Table 21-11. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode SPC0 = 0 MOSI MOSI Serial In SPI SPI Serial In MISO Serial Out Bidirectional Mode SPC0 = 1 Slave Mode MSTR = 0 MOMI Serial Out MISO Serial In BIDIROE SPI BIDIROE Serial In SPI Serial Out SISO The direction of each serial I/O pin depends on the BIDIROE bit.
PAGE 784
Chapter 21 Serial Peripheral Interface (S12SPIV5) the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state.
PAGE 785
Chapter 21 Serial Peripheral Interface (S12SPIV5) NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode.
PAGE 786
Chapter 21 Serial Peripheral Interface (S12SPIV5) 21.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 21.3.2.4, “SPI Status Register (SPISR)”. 21.4.7.5.3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced.
PAGE 787
Chapter 22 Timer Module (TIM16B8CV2) Block Description Table 22-1. Revision History Revision Number Revision Date V02.05 9 Jul 2009 22.3.2.12/22803 22.3.2.13/22803 22.3.2.15/22805 22.3.2.16/22806 22.3.2.19/22808 22.4.2/22-811 22.4.3/22-811 V02.06 26 Aug 2009 22.1.2/22-788 22.3.2.15/22805 22.3.2.2/22-794 22.3.2.3/22-795 22.3.2.4/22-796 22.4.3/22-811 V02.07 04 May 2010 22.3.2.8/22-799 - Add Table 22-10 22.3.2.11/22- - in TCRE bit description part,add Note - Add Figure 22-31 802 22.4.3/22-811 22.
PAGE 788
Chapter 22 Timer Module (TIM16B8CV2) Block Description A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. 22.1.1 Features The TIM16B8CV2 includes these distinctive features: • Eight input capture/output compare channels. • Clock prescaling. • 16-bit counter. • 16-bit pulse accumulator. 22.1.
PAGE 789
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.1.
PAGE 790
Chapter 22 Timer Module (TIM16B8CV2) Block Description TIMCLK (Timer clock) CLK1 CLK0 Intermodule Bus Clock select (PAMOD) Edge detector PT7 PACLK PACLK / 256 PACLK / 65536 Prescaled clock (PCLK) 4:1 MUX Interrupt PACNT MUX Divide by 64 M clock Figure 22-2. 16-Bit Pulse Accumulator Block Diagram 16-bit Main Timer PTn Edge detector Set CnF Interrupt TCn Input Capture Reg. Figure 22-3. Interrupt Flag Setting MC9S12XE-Family Reference Manual Rev. 1.
PAGE 791
Chapter 22 Timer Module (TIM16B8CV2) Block Description PULSE ACCUMULATOR PAD CHANNEL 7 OUTPUT COMPARE OCPD TEN TIOS7 Figure 22-4. Channel 7 Output Compare/Pulse Accumulator Logic 22.2 External Signal Description The TIM16B8CV2 module has a total of eight external pins. 22.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin This pin serves as input capture or output compare for channel 7. This can also be configured as pulse accumulator input. 22.2.
PAGE 792
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin This pin serves as input capture or output compare for channel 1. 22.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin This pin serves as input capture or output compare for channel 0. NOTE For the description of interrupts see Section 22.6, “Interrupts”. 22.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 22.3.
PAGE 793
Chapter 22 Timer Module (TIM16B8CV2) Block Description Register Name Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0x0006 TSCR1 R W TEN TSWAI TSFRZ TFFCA PRNT 0x0007 TTOV R W TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 0x0008 TCTL1 R W OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0x0009 TCTL2 R W OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0x000A TCTL3 R W EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0x000B TCTL4 R W EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0x000C TIE R W
PAGE 794
Chapter 22 Timer Module (TIM16B8CV2) Block Description Register Name 0x002C OCPD R W 0x002D R 0x002E PTPSR R W 0x002F Reserved R W Bit 7 6 5 4 3 2 1 Bit 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 = Unimplemented or Reserved Figure 22-5. TIM16B8CV2 Register Summary (Sheet 3 of 3) 22.3.2.
PAGE 795
Chapter 22 Timer Module (TIM16B8CV2) Block Description Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime Table 22-3. CFORC Field Descriptions Field Description 7:0 FOC[7:0] Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately.
PAGE 796
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.3.2.4 Output Compare 7 Data Register (OC7D) Module Base + 0x0003 7 6 5 4 3 2 1 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 R W Reset Figure 22-9. Output Compare 7 Data Register (OC7D) Read: Anytime Write: Anytime Table 22-5.
PAGE 797
Chapter 22 Timer Module (TIM16B8CV2) Block Description Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. 22.3.2.
PAGE 798
Chapter 22 Timer Module (TIM16B8CV2) Block Description Table 22-6. TSCR1 Field Descriptions (continued) Field Description 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag.
PAGE 799
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) Module Base + 0x0008 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 R W Reset Figure 22-14. Timer Control Register 1 (TCTL1) Module Base + 0x0009 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 R W Reset Figure 22-15. Timer Control Register 2 (TCTL2) Read: Anytime Write: Anytime Table 22-8.
PAGE 800
Chapter 22 Timer Module (TIM16B8CV2) Block Description To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the OC7M register must also be cleared. To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in the OC7M register must also be cleared. The settings for these bits can be seen in Table 22-10 Table 22-10.
PAGE 801
Chapter 22 Timer Module (TIM16B8CV2) Block Description Read: Anytime Write: Anytime. Table 22-11. TCTL3/TCTL4 Field Descriptions Field 7:0 EDGnB EDGnA Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits. Table 22-12. Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) 22.3.2.
PAGE 802
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.3.2.11 Timer System Control Register 2 (TSCR2) Module Base + 0x000D 7 R 6 5 4 0 0 0 TOI 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 22-19. Timer System Control Register 2 (TSCR2) Read: Anytime Write: Anytime. Table 22-14. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set.
PAGE 803
Chapter 22 Timer Module (TIM16B8CV2) Block Description NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. 22.3.2.12 Main Timer Interrupt Flag 1 (TFLG1) Module Base + 0x000E 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 R W Reset Figure 22-20.
PAGE 804
Chapter 22 Timer Module (TIM16B8CV2) Block Description Table 22-17. TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation.) 22.3.2.
PAGE 805
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) Module Base + 0x0020 7 R 6 5 4 3 2 1 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 W Reset 0 Unimplemented or Reserved Figure 22-24. 16-Bit Pulse Accumulator Control Register (PACTL) When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7. Read: Any time Write: Any time Table 22-18.
PAGE 806
Chapter 22 Timer Module (TIM16B8CV2) Block Description Table 22-19. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div. by 64 clock enabled with pin low level NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler. Table 22-20.
PAGE 807
Chapter 22 Timer Module (TIM16B8CV2) Block Description Table 22-21. PAFLG Field Descriptions Field Description 1 PAOVF Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.
PAGE 808
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.3.2.18 Output Compare Pin Disconnect Register(OCPD) Module Base + 0x002C 7 6 5 4 3 2 1 0 OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 0 0 0 0 0 0 0 0 R W Reset Figure 22-28. Ouput Compare Pin Disconnect Register (OCPD) Read: Anytime Write: Anytime All bits reset to zero. Table 22-22. OCPD Field Description Field OCPD[7:0} Description Output Compare Pin Disconnect Bits 0 Enables the timer channel port.
PAGE 809
Chapter 22 Timer Module (TIM16B8CV2) Block Description Table 22-23. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 22-24 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
PAGE 810
Chapter 22 Timer Module (TIM16B8CV2) Block Description Bus Clock CLK[1:0] PR[2:1:0] channel 7 output compare PACLK PACLK/256 PACLK/65536 MUX TCRE PRESCALER CxI TCNT(hi):TCNT(lo) CxF CLEAR COUNTER 16-BIT COUNTER TOF INTERRUPT LOGIC TOI TE TOF CHANNEL 0 16-BIT COMPARATOR OM:OL0 TC0 EDG0A C0F C0F EDGE DETECT EDG0B CH. 0 CAPTURE IOC0 PIN LOGIC CH. 0COMPARE TOV0 IOC0 PIN IOC0 CHANNEL 1 16-BIT COMPARATOR EDG1A C1F C1F OM:OL1 TC1 EDGE DETECT EDG1B CH. 1 CAPTURE IOC1 PIN LOGIC CH.
PAGE 811
Chapter 22 Timer Module (TIM16B8CV2) Block Description The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced.
PAGE 812
Chapter 22 Timer Module (TIM16B8CV2) Block Description Note: in Figure 22-31, if PR[2:0] is equal to 0, one prescaler counter is equal to one bus clock Figure 22-31. The TCNT cycle diagram under TCRE=1 condition prescaler counter TC7 1 bus clock 0 1 TC7-1 TC7 0 TC7 event TC7 event 22.4.3.1 ----- OC Channel Initialization Internal register whose output drives OCx can be programmed before timer drives OCx.
PAGE 813
Chapter 22 Timer Module (TIM16B8CV2) Block Description NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear. 22.4.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock.
PAGE 814
Chapter 22 Timer Module (TIM16B8CV2) Block Description 22.6.1 Channel [7:0] Interrupt (C[7:0]F) This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be serviced by the system controller. 22.6.2 Pulse Accumulator Input Interrupt (PAOVI) This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller. 22.6.
PAGE 815
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-1. Revision History Revision Number Revision Date V01.02 09 Sep 2005 23.3.2.3/23-822 - Updates for API external access and LVR flags. V01.03 23 Sep 2005 23.3.2.1/23-820 - VAE reset value is 1. V01.04 08 Jun 2007 23.1 Sections Affected 23.4.6/23-827 Description of Changes - Added temperature sensor to customer information Introduction Module VREG_3V3 is a tri output voltage regulator that provides two separate 1.
PAGE 816
Chapter 23 Voltage Regulator (S12VREGL3V3V1) 3. Shutdown mode Controlled by VREGEN (see device level specification for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a highimpedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API internal RC oscillator clock is not available. This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the VREG_3V3 to use external supplies. 23.1.
PAGE 817
Chapter 23 Voltage Regulator (S12VREGL3V3V1) VBG VDDPLL REG3 VSSPLL REG VDDR VDDA VDDF REG2 VSSA VDD REG1 VSS LVD LVR LVR POR POR VDDX C HTD VREGEN CTRL API Rate Select HTI LVI API API Bus Clock LVD: Low Voltage Detect REG: Regulator Core LVR: Low Voltage Reset CTRL: Regulator Control POR: Power-on Reset API: Auto. Periodical Interrupt HTD: High Temperature Detect PIN Figure 23-1. VREG_3V3 Block Diagram MC9S12XE-Family Reference Manual Rev. 1.
PAGE 818
Chapter 23 Voltage Regulator (S12VREGL3V3V1) 23.2 External Signal Description Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. Table 23-2 shows all signals of VREG_3V3 associated with pins. Table 23-2.
PAGE 819
Chapter 23 Voltage Regulator (S12VREGL3V3V1) 23.2.4 VDDF — Regulator Output2 (NVM Logic) Pins Signals VDDF/VSS are the secondary outputs of VREG_3V3 that provide the power supply for the NVM logic. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic). In Shutdown Mode an external supply driving VDDF/VSS can replace the voltage regulator. 23.2.
PAGE 820
Chapter 23 Voltage Regulator (S12VREGL3V3V1) 23.3.1 Module Memory Map A summary of the registers associated with the VREG_3V3 sub-block is shown in Figure 23-2. Detailed descriptions of the registers and bits are given in the subsections that follow Figure 23-2.
PAGE 821
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-3. VREGHTCL Field Descriptions Field 7, 6 Reserved Description These reserved bits are used for test purposes and writable only in special modes. They must remain clear for correct temperature sensor operation. 5 VSEL Voltage Access Select Bit — If set, the bandgap reference voltage VBG can be accessed internally (i.e. multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabled by bit VAE.
PAGE 822
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-4. VREGCTRL Field Descriptions Field Description 2 LVDS Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect. 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode. 1 Input voltage VDDA is below level VLVIA and FPM. 1 LVIE Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set.
PAGE 823
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-5. VREGAPICL Field Descriptions (continued) Field Description 1 APIE Autonomous Periodical Interrupt Enable Bit 0 API interrupt request is disabled. 1 API interrupt will be requested whenever APIF is set. 0 APIF Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed. This flag can only be cleared by writing a 1 to it. Clearing of the flag has precedence over setting. Writing a 0 has no effect.
PAGE 824
Chapter 23 Voltage Regulator (S12VREGL3V3V1) 0x02F4 R W Reset 7 6 5 4 3 2 1 0 APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 23-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH) 0x02F5 R W Reset 7 6 5 4 3 2 1 0 APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 0 0 0 0 0 0 0 0 Figure 23-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL) Table 23-8.
PAGE 825
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-9. Selectable Autonomous Periodical Interrupt Periods (continued) APICLK APIR[15:0] Selected Period 1 FFFF 131072 * bus clock period 1. When trimmed within specified accuracy. See electrical specifications for details. The period can be calculated as follows depending of APICLK: Period = 2*(APIR[15:0] + 1) * 0.1 ms or period = 2*(APIR[15:0] + 1) * bus clock period 23.3.2.6 Reserved 06 The Reserved 06 is reserved for test purposes.
PAGE 826
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-11. Trimming Effect (continued) Bit 23.4 Trimming Effect HTTR[2] Increases VHT twice of HTTR[1] HTTR[1] Increases VHT twice of HTTR[0] HTTR[0] Increases VHT (to compensate Temperature Offset) Functional Description 23.4.1 General Module VREG_3V3 is a voltage regulator, as depicted in Figure 23-1.
PAGE 827
Chapter 23 Voltage Regulator (S12VREGL3V3V1) 23.4.4 Power-On Reset (POR) This functional block monitors VDD. If VDD is below VPORD, POR is asserted; if VDD exceeds VPORD, the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the poweron sequence. 23.4.5 Low-Voltage Reset (LVR) Block LVR monitors the supplies VDD, VDDX and VDDF.
PAGE 828
Chapter 23 Voltage Regulator (S12VREGL3V3V1) The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See Table 23-7 for the trimming effect of APITR. NOTE The first period after enabling the counter by APIFE might be reduced by API start up delay tsdel. The API internal RC oscillator clock is not available if VREG_3V3 is in Shutdown Mode.
PAGE 829
Chapter 23 Voltage Regulator (S12VREGL3V3V1) Table 23-13. Interrupt Vectors Interrupt Source Local Enable Low-voltage interrupt (LVI) LVIE = 1; available only in Full Performance Mode High Temperature Interrupt (HTI) HTIE=1; available only in Full Performance Mode Autonomous periodical interrupt (API) APIE = 1 23.4.11.1 Low-Voltage Interrupt (LVI) In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1.
PAGE 830
Chapter 23 Voltage Regulator (S12VREGL3V3V1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 831
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-1. Revision History Revision Number Revision Date Sections Affected V01.10 30 Nov 2007 24.1.3/24-834 V01.11 19 Dec 2007 24.4.2/24-867 24.4.2/24-867 - Removed Load Data Field command 0x05 - Updated Command Error Handling tables based on parent-child relationship with FTM256K2 24.4.2/24-867 - Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash, and EEPROM Emulation Query commands 24.4.
PAGE 832
24.
PAGE 833
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE. Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile memory space for applications. D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
PAGE 834
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) • • • • Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Ability to program up to four words in a burst sequence 24.1.2.
PAGE 835
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Flash Interface Command Interrupt Request Registers Error Interrupt Request Protection 16bit internal bus P-Flash Block 0 8Kx72 sector 0 sector 1 sector 63 Security Oscillator Clock (XTAL) XGATE CPU P-Flash Block 1 8Kx72 Clock Divider FCLK sector 0 sector 1 Memory Controller Scratch RAM 512x16 Buffer RAM 1Kx16 sector 63 D-Flash 16Kx22 sector 0 sector 1 sector 127 Tag RAM 64x16 Figure 24-1. FTM128K2 Block Diagram 24.
PAGE 836
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 24.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF as shown in Table 24-2.
PAGE 837
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-3. Flash Configuration Field(1) Global Address Size (Bytes) Description Flash Security byte Refer to Section 24.3.2.2, “Flash Security Register (FSEC)” 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
PAGE 838
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) P-Flash START = 0x78_0000 0x78_FFFF Flash Protected/Unprotected Region 96 Kbytes 0x7F_0000 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figu
PAGE 839
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 24.4.2.6, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 24-5.
PAGE 840
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) D-Flash START = 0x10_0000 D-Flash User Partition D-Flash Memory 32 Kbytes D-Flash EEE Partition D-Flash END = 0x10_7FFF 0x12_0000 0x12_1000 0x12_2000 0x12_4000 EEE Nonvolatile Information Register (EEEIFRON) 128 bytes EEE Tag RAM (TMGRAMON) 128 bytes Memory Controller Scratch RAM (TMGRAMON) 1024 bytes 0x12_E000 0x12_FFFF Buffer RAM START = 0x13_F800 Buffer RAM User Partition 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_FF
PAGE 841
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) The Full Partition D-Flash command (see Section 24.4.2.14) is used to program the EEE nonvolatile information register fields where address 0x12_0000 defines the D-Flash partition for user access and address 0x12_0004 defines the buffer RAM partition for EEE operations. Table 24-7. EEE Nonvolatile Information Register Fields Global Address (EEEIFRON) Size (Bytes) 0x12_0000 – 0x12_0001 2 D-Flash User Partition (DFPART) Refer to Section 24.4.2.
PAGE 842
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Address & Name 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C ETAGHI 0x000D ETAGLO 0x000E FECCRHI 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 7 6 ERSERIE PGMERIE R 5 4 3 2 1 0 EPVIOLIE ERSVIE1 ERSVIE0 DFDIE SFDIE MGBUSY RSVD MGSTAT1 MGSTAT0 EPVIOLIF ERSVIF1 ERSVIF0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 0 W R
PAGE 843
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Address & Name 0x0013 FRSV2 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 24-4. FTM128K2 Register Summary (continued) 24.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIV[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 24-5.
PAGE 844
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-9. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) MIN(1) FDIV[6:0] MAX(2) OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 33.60 34.65 0x20 67.20 68.25 0x40 1.60 2.10 0x01 34.65 35.70 0x21 68.25 69.30 0x41 2.40 3.15 0x02 35.70 36.75 0x22 69.30 70.35 0x42 3.20 4.20 0x03 36.75 37.80 0x23 70.35 71.40 0x43 4.20 5.25 0x04 37.80 38.85 0x24 71.40 72.
PAGE 845
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 2. FDIV shown generates an FCLK frequency of 1.05 MHz 24.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 24-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 846
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-12. Flash Security States SEC[1:0] Status of Security 00 SECURED 01 SECURED(1) 10 UNSECURED 11 SECURED 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 24.5. 24.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 847
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-14. FECCRIX Field Descriptions Field Description 2-0 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 24.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. 24.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE.
PAGE 848
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-15. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
PAGE 849
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-16. FERCNFG Field Descriptions (continued) Field Description 3 ERSVIE1 EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error is detected during an EEE operation. 0 ERSVIF1 interrupt disabled 1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 24.3.2.
PAGE 850
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-17. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 851
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-18. FERSTAT Field Descriptions Field Description 7 ERSERIF EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF.
PAGE 852
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 24-13. Flash Protection Register (FPROT) The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 24.3.2.9.1, “P-Flash Protection Restrictions,” and Table 24-23).
PAGE 853
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-20. P-Flash Protection Function Function(1) FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1. For range sizes, refer to Table 24-21 and Table 24-22. Table 24-21.
PAGE 854
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 24-14.
PAGE 855
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 24-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 24-23.
PAGE 856
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected. Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection violation error and the EPVIOLIF flag will be set in the FERSTAT register.
PAGE 857
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 24-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 24-17. Flash Common Command Object Low Register (FCCOBLO) 24.3.2.11.
PAGE 858
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 24.3.2.12 EEE Tag Counter Register (ETAG) The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need to be programmed into the D-Flash EEE partition.
PAGE 859
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults, the priority for fault recording is: 1. Double bit fault over single bit fault 2. CPU over XGATE Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 24-20.
PAGE 860
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-28. FECCR Index=000 Bit Descriptions Field Description 15:8 PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits, allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00. 7 XBUS01 Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access from the CPU or XGATE.
PAGE 861
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-23. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 24.3.2.16 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 862
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4 Functional Description 24.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents or configure module resources for EEE operation.
PAGE 863
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.1.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 24.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 864
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 865
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.1.3 Valid Flash Module Commands Table 24-30.
PAGE 866
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.1.4 P-Flash Commands Table 24-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module. Table 24-31.
PAGE 867
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-32. D-Flash Commands FCMD Command Function on D-Flash Memory 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D-Flash (and P-Flash) blocks and verifying that all D-Flash (and P-Flash) blocks are erased. 0x0D Set User Margin Level Specifies a user margin read level for the D-Flash block. 0x0E Set Field Margin Level Specifies a field margin read level for the D-Flash block (special modes only).
PAGE 868
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.2.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 24-33. Erase Verify All Blocks Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x01 Not required Upon clearing CCIF to launch the Erase Verify All Blocks command, the Memory Controller will verify that the entire Flash memory space is erased.
PAGE 869
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-36. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR FPVIOL FSTAT Set if an invalid global address [22:16] is supplied(1) None MGSTAT1 Set if any errors have been encountered during the read(2) MGSTAT0 Set if any non-correctable errors have been encountered during the read2 FERSTAT EPVIOLIF None 1. As defined by the memory map for FTM256K2. 2.
PAGE 870
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 1. As defined by the memory map for FTM256K2. 2. As found in the memory map for FTM256K2. 24.4.2.4 Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the Program Once command described in Section 24.4.2.6.
PAGE 871
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 24-41.
PAGE 872
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 24-43.
PAGE 873
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-45. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released.
PAGE 874
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-48.
PAGE 875
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.2.10 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is successful, will release security. Table 24-51. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and D-Flash memory space and verify that it is erased.
PAGE 876
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-53. Verify Backdoor Access Key Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 011 Key 2 100 Key 3 Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates.
PAGE 877
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Valid margin level settings for the Set User Margin Level command are defined in Table 24-56. Table 24-56. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level(1) 0x0002 User Margin-0 Level(2) 1. Read margin to the erased state 2. Read margin to the programmed state Table 24-57.
PAGE 878
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Upon clearing CCIF to launch the Set Field Margin Level command, the Memory Controller will set the field margin level for the targeted block and then set the CCIF flag. Valid margin level settings for the Set Field Margin Level command are defined in Table 24-59. Table 24-59.
PAGE 879
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.2.14 Full Partition D-Flash Command The Full Partition D-Flash command allows the user to allocate sectors within the D-Flash block for applications and a partition within the buffer RAM for EEPROM access. The D-Flash block consists of 128 sectors with 256 bytes per sector. Table 24-61.
PAGE 880
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-62.
PAGE 881
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-64.
PAGE 882
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-66.
PAGE 883
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-68.
PAGE 884
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.2.19 Disable EEPROM Emulation Command The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE activity. Table 24-71.
PAGE 885
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Table 24-74. EEPROM Emulation Query Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if command not available in current mode (see Table 24-30) FSTAT FERSTAT FPVIOL None MGSTAT1 None MGSTAT0 None EPVIOLIF None 24.4.2.
PAGE 886
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) • • Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 24-7) Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 24-7) The D-Flash user partition will start at global address 0x10_0000. The buffer RAM EEE partition will end at global address 0x13_FFFF. After the Partition D-Flash operation has completed, the CCIF flag will set.
PAGE 887
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) 24.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. Table 24-77.
PAGE 888
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) Flash Command Interrupt Request CCIE CCIF ERSERIE ERSERIF PGMERIE PGMERIF EPVIOLIE EPVIOLIF Flash Error Interrupt Request ERSVIE1 ERSVIF1 ERSVIE0 ERSVIF0 DFDIE DFDIF SFDIE SFDIF Figure 24-27. Flash Module Interrupts Implementation 24.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 24.4.3, “Interrupts”). 24.4.
PAGE 889
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) The security state out of reset can be permanently changed by programming the security byte of the Flash configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
PAGE 890
Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) (0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. 24.5.
PAGE 891
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-1. Revision History Revision Number Revision Date Sections Affected V01.08 14 Nov 2007 25.5.2/25-951 - Changed terminology from ‘word program’ to “Program P-Flash’ in the BDM unsecuring description, Section 25.5.2 25.4.2/25-927 - Added requirement that user not write any Flash module register during execution of commands ‘Erase All Blocks’, Section 25.4.2.8, and ‘Unsecure Flash’, Section 25.4.2.11 25.4.2.
PAGE 892
• • 32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic Flash memory primarily intended for nonvolatile data storage, or as a combination of both 4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both The Flash memory is ideal for single-supply applicati
PAGE 893
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased. The D-Flash sector consists of four 64 byte rows for a total of 256 bytes. EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance characteristics associated with an EEPROM.
PAGE 894
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.1.2.
PAGE 895
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Flash Interface Command Interrupt Request Registers Error Interrupt Request Protection 16bit internal bus P-Flash Block 0 16Kx72 sector 0 sector 1 sector 127 Security Oscillator Clock (XTAL) XGATE CPU P-Flash Block 1 16Kx72 Clock Divider FCLK sector 0 sector 1 Memory Controller Scratch RAM 512x16 Buffer RAM 2Kx16 sector 127 D-Flash 16Kx22 sector 0 sector 1 sector 127 Tag RAM 128x16 Figure 25-1. FTM256K2 Block Diagram 25.
PAGE 896
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 25.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF as shown in Table 25-2.
PAGE 897
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-3. Flash Configuration Field(1) Global Address Size (Bytes) Description Flash Security byte Refer to Section 25.3.2.2, “Flash Security Register (FSEC)” 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
PAGE 898
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) P-Flash START = 0x78_0000 0x79_FFFF Flash Protected/Unprotected Region 224 Kbytes 0x7E_0000 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Fig
PAGE 899
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 25.4.2.7, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 25-5.
PAGE 900
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) D-Flash START = 0x10_0000 D-Flash User Partition D-Flash Memory 32 Kbytes D-Flash EEE Partition D-Flash END = 0x10_7FFF 0x12_0000 0x12_1000 0x12_2000 0x12_4000 EEE Nonvolatile Information Register (EEEIFRON) 128 bytes EEE Tag RAM (TMGRAMON) 256 bytes Memory Controller Scratch RAM (TMGRAMON) 1024 bytes 0x12_E000 0x12_FFFF Buffer RAM START = 0x13_F000 Buffer RAM User Partition 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_FF
PAGE 901
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-7. EEE Nonvolatile Information Register Fields Global Address (EEEIFRON) Size (Bytes) 0x12_0000 – 0x12_0001 2 D-Flash User Partition (DFPART) Refer to Section 25.4.2.15, “Full Partition D-Flash Command” 0x12_0002 – 0x12_0003 2 D-Flash User Partition (duplicate(1)) 0x12_0004 – 0x12_0005 2 Buffer RAM EEE Partition (ERPART) Refer to Section 25.4.2.
PAGE 902
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Address & Name 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C ETAGHI 0x000D ETAGLO 0x000E FECCRHI 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 7 6 R 5 4 3 2 1 0 ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 EPVIOLIF ERSVIF1 ERSVIF0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 0 CCIF W R 0 ERSERIF PGMERIF W R RNV6 FPOPEN W R
PAGE 903
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Address & Name 7 6 5 4 3 2 1 0 = Unimplemented or Reserved Figure 25-4. FTM256K2 Register Summary (continued) 25.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIV[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 25-5.
PAGE 904
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-9. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) MIN(1) FDIV[6:0] MAX(2) OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 33.60 34.65 0x20 67.20 68.25 0x40 1.60 2.10 0x01 34.65 35.70 0x21 68.25 69.30 0x41 2.40 3.15 0x02 35.70 36.75 0x22 69.30 70.35 0x42 3.20 4.20 0x03 36.75 37.80 0x23 70.35 71.40 0x43 4.20 5.25 0x04 37.80 38.85 0x24 71.40 72.
PAGE 905
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 2. FDIV shown generates an FCLK frequency of 1.05 MHz 25.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 25-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 906
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-12. Flash Security States SEC[1:0] Status of Security 00 SECURED 01 SECURED(1) 10 UNSECURED 11 SECURED 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 25.5. 25.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 907
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-14. FECCRIX Field Descriptions Field Description 2-0 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 25.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. 25.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE.
PAGE 908
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-15. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
PAGE 909
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-16. FERCNFG Field Descriptions (continued) Field Description 3 ERSVIE1 EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error is detected during an EEE operation. 0 ERSVIF1 interrupt disabled 1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 25.3.2.
PAGE 910
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-17. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 911
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-18. FERSTAT Field Descriptions Field Description 7 ERSERIF EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF.
PAGE 912
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 25-13. Flash Protection Register (FPROT) The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 25.3.2.9.1, “P-Flash Protection Restrictions,” and Table 25-23).
PAGE 913
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-20. P-Flash Protection Function Function(1) FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1. For range sizes, refer to Table 25-21 and Table 25-22. Table 25-21.
PAGE 914
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 25-14.
PAGE 915
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 25-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 25-23.
PAGE 916
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected. Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection violation error and the EPVIOLIF flag will be set in the FERSTAT register.
PAGE 917
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 25-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 25-17. Flash Common Command Object Low Register (FCCOBLO) 25.3.2.11.
PAGE 918
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 25.3.2.12 EEE Tag Counter Register (ETAG) The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need to be programmed into the D-Flash EEE partition.
PAGE 919
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults, the priority for fault recording is: 1. Double bit fault over single bit fault 2. CPU over XGATE Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 25-20.
PAGE 920
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-28. FECCR Index=000 Bit Descriptions Field Description 15:8 PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits, allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00. 7 XBUS01 Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access from the CPU or XGATE.
PAGE 921
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-23. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 25.3.2.16 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 922
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4 Functional Description 25.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents or configure module resources for EEE operation.
PAGE 923
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4.1.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 25.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 924
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 925
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4.1.3 Valid Flash Module Commands Table 25-30.
PAGE 926
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4.1.4 P-Flash Commands Table 25-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module. Table 25-31. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify PFlash Section 0x04 Read Once 0x05 Load Data Field Load data for simultaneous multiple P-Flash block operations.
PAGE 927
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-32. D-Flash Commands FCMD Command Function on D-Flash Memory 0x08 Erase All Blocks Erase all D-Flash (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command.
PAGE 928
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 25.4.2.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 25-33.
PAGE 929
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-36. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if an invalid global address [22:16] is supplied FSTAT FPVIOL FERSTAT 25.4.2.
PAGE 930
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-38. Erase Verify P-Flash Section Command Error Handling Register Error Bit FERSTAT EPVIOLIF 25.4.2.4 Error Condition None Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the Program Once command described in Section 25.4.2.7.
PAGE 931
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-41. Load Data Field Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x05 Global address [22:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed(1) 010 Word 0 011 Word 1 100 Word 2 101 1.
PAGE 932
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 25-43.
PAGE 933
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 25-45.
PAGE 934
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-47. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released.
PAGE 935
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-50.
PAGE 936
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4.2.11 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is successful, will release security. Table 25-53. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and D-Flash memory space and verify that it is erased.
PAGE 937
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x7F_FF00, etc.
PAGE 938
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-58. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0002 User Margin-0 Level(2) 1. Read margin to the erased state 2. Read margin to the programmed state Table 25-59.
PAGE 939
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Valid margin level settings for the Set Field Margin Level command are defined in Table 25-61. Table 25-61. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level(1) 0x0002 User Margin-0 Level(2) 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1. Read margin to the erased state 2. Read margin to the programmed state Table 25-62.
PAGE 940
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-63.
PAGE 941
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-64.
PAGE 942
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-66.
PAGE 943
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-68.
PAGE 944
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-70.
PAGE 945
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4.2.20 Disable EEPROM Emulation Command The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE activity. Table 25-73.
PAGE 946
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Table 25-76. EEPROM Emulation Query Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if command not available in current mode (see Table 25-30) FSTAT FERSTAT FPVIOL None MGSTAT1 None MGSTAT0 None EPVIOLIF None 25.4.2.
PAGE 947
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) • • • Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 (see Table 25-7) Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 25-7) Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 25-7) The D-Flash user partition will start at global address 0x10_0000.
PAGE 948
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) 25.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. Table 25-79.
PAGE 949
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) Flash Command Interrupt Request CCIE CCIF ERSERIE ERSERIF PGMERIE PGMERIF EPVIOLIE EPVIOLIF Flash Error Interrupt Request ERSVIE1 ERSVIF1 ERSVIE0 ERSVIF0 DFDIE DFDIF SFDIE SFDIF Figure 25-27. Flash Module Interrupts Implementation 25.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 25.4.3, “Interrupts”). 25.4.
PAGE 950
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) The security state out of reset can be permanently changed by programming the security byte of the Flash configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
PAGE 951
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) (0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. 25.5.
PAGE 952
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 953
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-1. Revision History Revision Number Revision Date V01.10 29 Nov 2007 V01.11 19 Dec 2007 Sections Affected - Cleanup 26.4.2/26-989 26.4.2/26-989 26.3.1/26-958 V01.12 26.
PAGE 954
• 4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents or configure module resources for emulated EEPROM operation.
PAGE 955
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance characteristics associated with an EEPROM. EEE IFR — Nonvolatile information register located in the D-Flash block that contains data required to partition the D-Flash memory and buffer RAM for EEE. The EEE IFR is visible in the global memory map by setting the EEEIFRON bit in the MMCCTL1 register.
PAGE 956
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.1.2.
PAGE 957
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Flash Interface Command Interrupt Request Registers Error Interrupt Request Protection 16bit internal bus P-Flash Block 0 32Kx72 16Kx72 16Kx72 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127 Security Oscillator Clock (XTAL) P-Flash Block 1 16Kx72 Clock Divider FCLK XGATE sector 0 sector 1 Memory Controller CPU Scratch RAM 512x16 Buffer RAM 2Kx16 sector 127 D-Flash 16Kx22 sector 0 sector 1 sector 127 Tag RAM 128x16 Figure 26-1.
PAGE 958
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 26.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF as shown in Table 26-2.
PAGE 959
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-3. Flash Configuration Field(1) Global Address Size (Bytes) Description Flash Security byte Refer to Section 26.3.2.2, “Flash Security Register (FSEC)” 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
PAGE 960
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) P-Flash START = 0x78_0000 0x79_FFFF Flash Protected/Unprotected Region 352 Kbytes 0x7C_0000 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Fig
PAGE 961
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 26.4.2.7, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 26-5.
PAGE 962
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) D-Flash START = 0x10_0000 D-Flash User Partition D-Flash Memory 32 Kbytes D-Flash EEE Partition D-Flash END = 0x10_7FFF 0x12_0000 0x12_1000 0x12_2000 0x12_4000 EEE Nonvolatile Information Register (EEEIFRON) 128 bytes EEE Tag RAM (TMGRAMON) 256 bytes Memory Controller Scratch RAM (TMGRAMON) 1024 bytes 0x12_E000 0x12_FFFF Buffer RAM START = 0x13_F000 Buffer RAM User Partition 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_FF
PAGE 963
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-7. EEE Nonvolatile Information Register Fields Global Address (EEEIFRON) Size (Bytes) 0x12_0000 – 0x12_0001 2 D-Flash User Partition (DFPART) Refer to Section 26.4.2.15, “Full Partition D-Flash Command” 0x12_0002 – 0x12_0003 2 D-Flash User Partition (duplicate(1)) 0x12_0004 – 0x12_0005 2 Buffer RAM EEE Partition (ERPART) Refer to Section 26.4.2.
PAGE 964
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Address & Name 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C ETAGHI 0x000D ETAGLO 0x000E FECCRHI 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 7 6 R 5 4 3 2 1 0 ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 EPVIOLIF ERSVIF1 ERSVIF0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 0 CCIF W R 0 ERSERIF PGMERIF W R RNV6 FPOPEN W R
PAGE 965
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Address & Name 7 6 5 4 3 2 1 0 = Unimplemented or Reserved Figure 26-4. FTM384K2 Register Summary (continued) 26.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIV[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 26-5.
PAGE 966
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-9. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) MIN(1) FDIV[6:0] MAX(2) OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 33.60 34.65 0x20 67.20 68.25 0x40 1.60 2.10 0x01 34.65 35.70 0x21 68.25 69.30 0x41 2.40 3.15 0x02 35.70 36.75 0x22 69.30 70.35 0x42 3.20 4.20 0x03 36.75 37.80 0x23 70.35 71.40 0x43 4.20 5.25 0x04 37.80 38.85 0x24 71.40 72.
PAGE 967
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 2. FDIV shown generates an FCLK frequency of 1.05 MHz 26.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 26-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 968
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-12. Flash Security States SEC[1:0] Status of Security 00 SECURED 01 SECURED(1) 10 UNSECURED 11 SECURED 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 26.5. 26.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 969
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-14. FECCRIX Field Descriptions Field Description 2-0 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 26.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. 26.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE.
PAGE 970
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-15. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
PAGE 971
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-16. FERCNFG Field Descriptions (continued) Field Description 3 ERSVIE1 EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error is detected during an EEE operation. 0 ERSVIF1 interrupt disabled 1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 26.3.2.
PAGE 972
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-17. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 973
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-18. FERSTAT Field Descriptions Field Description 7 ERSERIF EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF.
PAGE 974
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 26-13. Flash Protection Register (FPROT) The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 26.3.2.9.1, “P-Flash Protection Restrictions,” and Table 26-23).
PAGE 975
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-20. P-Flash Protection Function Function(1) FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1. For range sizes, refer to Table 26-21 and Table 26-22. Table 26-21.
PAGE 976
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 26-14.
PAGE 977
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 26-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 26-23.
PAGE 978
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected. Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection violation error and the EPVIOLIF flag will be set in the FERSTAT register.
PAGE 979
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 26-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 26-17. Flash Common Command Object Low Register (FCCOBLO) 26.3.2.11.
PAGE 980
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 26.3.2.12 EEE Tag Counter Register (ETAG) The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need to be programmed into the D-Flash EEE partition.
PAGE 981
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults, the priority for fault recording is: 1. Double bit fault over single bit fault 2. CPU over XGATE Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 26-20.
PAGE 982
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-28. FECCR Index=000 Bit Descriptions Field Description 15:8 PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits, allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00. 7 XBUS01 Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access from the CPU or XGATE.
PAGE 983
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-23. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 26.3.2.16 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 984
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4 Functional Description 26.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents or configure module resources for EEE operation.
PAGE 985
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4.1.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 26.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 986
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 987
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4.1.3 Valid Flash Module Commands Table 26-30.
PAGE 988
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4.1.4 P-Flash Commands Table 26-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module. Table 26-31. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify PFlash Section 0x04 Read Once 0x05 Load Data Field Load data for simultaneous multiple P-Flash block operations.
PAGE 989
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-32. D-Flash Commands FCMD Command Function on D-Flash Memory 0x08 Erase All Blocks Erase all D-Flash (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command.
PAGE 990
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 26.4.2.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 26-33.
PAGE 991
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-36. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if an invalid global address [22:16] is supplied(1) FSTAT FPVIOL None MGSTAT1 Set if any errors have been encountered during the read(2) MGSTAT0 Set if any non-correctable errors have been encountered during the read2 FERSTAT EPVIOLIF None 1.
PAGE 992
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-38.
PAGE 993
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-40. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if a Load Data Field command sequence is currently active ACCERR Set if command not available in current mode (see Table 26-30) FSTAT Set if an invalid phrase index is supplied FPVIOL FERSTAT 26.4.2.
PAGE 994
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-42.
PAGE 995
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-44.
PAGE 996
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. Table 26-46.
PAGE 997
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-48.
PAGE 998
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4.2.10 Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 26-51. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0A Global address [22:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 26.1.2.1 for the P-Flash sector size.
PAGE 999
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 26-54.
PAGE 1000
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-56. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if a Load Data Field command sequence is currently active ACCERR Set if an incorrect backdoor key is supplied Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 26.3.2.
PAGE 1001
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-59. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if a Load Data Field command sequence is currently active ACCERR Set if command not available in current mode (see Table 26-30) Set if an invalid global address [22:16] is supplied(1) FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None 1.
PAGE 1002
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-61. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0002 User Margin-0 Level(2) 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1. Read margin to the erased state 2. Read margin to the programmed state Table 26-62.
PAGE 1003
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-63.
PAGE 1004
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-64.
PAGE 1005
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-66.
PAGE 1006
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-68.
PAGE 1007
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-70.
PAGE 1008
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4.2.20 Disable EEPROM Emulation Command The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE activity. Table 26-73.
PAGE 1009
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Table 26-76. EEPROM Emulation Query Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if command not available in current mode (see Table 26-30) FSTAT FERSTAT FPVIOL None MGSTAT1 None MGSTAT0 None EPVIOLIF None 26.4.2.
PAGE 1010
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) • • • Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 (see Table 26-7) Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 26-7) Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 26-7) The D-Flash user partition will start at global address 0x10_0000.
PAGE 1011
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) 26.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. Table 26-79.
PAGE 1012
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) Flash Command Interrupt Request CCIE CCIF ERSERIE ERSERIF PGMERIE PGMERIF EPVIOLIE EPVIOLIF Flash Error Interrupt Request ERSVIE1 ERSVIF1 ERSVIE0 ERSVIF0 DFDIE DFDIF SFDIE SFDIF Figure 26-27. Flash Module Interrupts Implementation 26.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 26.4.3, “Interrupts”). 26.4.
PAGE 1013
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) The security state out of reset can be permanently changed by programming the security byte of the Flash configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
PAGE 1014
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) (0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. 26.5.
PAGE 1015
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-1. Revision History Revision Number Revision Date Sections Affected V01.09 14 Nov 2007 27.5.2/27-1075 - Changed terminology from ‘word program’ to “Program P-Flash’ in the BDM unsecuring description, Section 27.5.2 27.4.2/27-1051 - Added requirement that user not write any Flash module register during execution of commands ‘Erase All Blocks’, Section 27.4.2.8, and ‘Unsecure Flash’, Section 27.4.2.
PAGE 1016
27.
PAGE 1017
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE. Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile memory space for applications. D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased.
PAGE 1018
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.1.2.2 • • • • • • Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access Dedicated commands to control access to the D-Flash memory over EEE operation Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Ability to program up to four words in a burst sequence 27.1.
PAGE 1019
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 16bit internal bus Flash Interface P-Flash Block 0 32Kx72 16Kx72 16Kx72 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127 Command Interrupt Request Registers Error Interrupt Request Protection P-Flash Block 1N 16Kx72 Security sector 127 Oscillator Clock (XTAL) sector 0 sector 1 P-Flash Block 1S 16Kx72 Clock Divider FCLK XGATE sector 0 sector 1 Memory Controller CPU Scratch RAM 512x16 Buffer RAM 2Kx16 sector 127 D-Flash 16Kx22
PAGE 1020
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 27.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x78_0000 and 0x7F_FFFF as shown in Table 27-2.
PAGE 1021
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-3. Flash Configuration Field(1) Global Address Size (Bytes) Description Flash Security byte Refer to Section 27.3.2.2, “Flash Security Register (FSEC)” 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x7F_FF08 - 0x7F_FF0B reserved field should be programmed to 0xFF.
PAGE 1022
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) P-Flash START = 0x78_0000 Flash Protected/Unprotected Region 480 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 27-2.
PAGE 1023
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 27.4.2.7, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 27-5.
PAGE 1024
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) D-Flash START = 0x10_0000 D-Flash User Partition D-Flash Memory 32 Kbytes D-Flash EEE Partition D-Flash END = 0x10_7FFF 0x12_0000 0x12_1000 0x12_2000 0x12_4000 EEE Nonvolatile Information Register (EEEIFRON) 128 bytes EEE Tag RAM (TMGRAMON) 256 bytes Memory Controller Scratch RAM (TMGRAMON) 1024 bytes 0x12_E000 0x12_FFFF Buffer RAM START = 0x13_F000 Buffer RAM User Partition 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_FF
PAGE 1025
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-7. EEE Nonvolatile Information Register Fields Global Address (EEEIFRON) Size (Bytes) 0x12_0000 – 0x12_0001 2 D-Flash User Partition (DFPART) Refer to Section 27.4.2.15, “Full Partition D-Flash Command” 0x12_0002 – 0x12_0003 2 D-Flash User Partition (duplicate(1)) 0x12_0004 – 0x12_0005 2 Buffer RAM EEE Partition (ERPART) Refer to Section 27.4.2.
PAGE 1026
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Address & Name 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C ETAGHI 0x000D ETAGLO 0x000E FECCRHI 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 7 6 R 5 4 3 2 1 0 ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 EPVIOLIF ERSVIF1 ERSVIF0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 0 CCIF W R 0 ERSERIF PGMERIF W R RNV6 FPOPEN W R
PAGE 1027
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Address & Name 7 6 5 4 3 2 1 0 = Unimplemented or Reserved Figure 27-4. FTM512K3 Register Summary (continued) 27.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIV[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 27-5.
PAGE 1028
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-9. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) MIN(1) FDIV[6:0] MAX(2) OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 33.60 34.65 0x20 67.20 68.25 0x40 1.60 2.10 0x01 34.65 35.70 0x21 68.25 69.30 0x41 2.40 3.15 0x02 35.70 36.75 0x22 69.30 70.35 0x42 3.20 4.20 0x03 36.75 37.80 0x23 70.35 71.40 0x43 4.20 5.25 0x04 37.80 38.85 0x24 71.40 72.
PAGE 1029
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 2. FDIV shown generates an FCLK frequency of 1.05 MHz 27.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 27-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 1030
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-12. Flash Security States SEC[1:0] Status of Security 00 SECURED 01 SECURED(1) 10 UNSECURED 11 SECURED 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 27.5. 27.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 1031
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-14. FECCRIX Field Descriptions Field Description 2-0 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 27.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. 27.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE.
PAGE 1032
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-15. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
PAGE 1033
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-16. FERCNFG Field Descriptions (continued) Field Description 3 ERSVIE1 EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error is detected during an EEE operation. 0 ERSVIF1 interrupt disabled 1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 27.3.2.
PAGE 1034
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-17. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 1035
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-18. FERSTAT Field Descriptions Field Description 7 ERSERIF EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF.
PAGE 1036
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 27-13. Flash Protection Register (FPROT) The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 27.3.2.9.1, “P-Flash Protection Restrictions,” and Table 27-23).
PAGE 1037
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-20. P-Flash Protection Function Function(1) FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1. For range sizes, refer to Table 27-21 and Table 27-22. Table 27-21.
PAGE 1038
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 27-14.
PAGE 1039
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 27-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 27-23.
PAGE 1040
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected. Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection violation error and the EPVIOLIF flag will be set in the FERSTAT register.
PAGE 1041
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 27-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 27-17. Flash Common Command Object Low Register (FCCOBLO) 27.3.2.11.
PAGE 1042
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 27.3.2.12 EEE Tag Counter Register (ETAG) The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need to be programmed into the D-Flash EEE partition.
PAGE 1043
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults, the priority for fault recording is: 1. Double bit fault over single bit fault 2. CPU over XGATE Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 27-20.
PAGE 1044
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-28. FECCR Index=000 Bit Descriptions Field Description 15:8 PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits, allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00. 7 XBUS01 Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access from the CPU or XGATE.
PAGE 1045
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-23. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 27.3.2.16 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 1046
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4 Functional Description 27.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents or configure module resources for EEE operation.
PAGE 1047
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4.1.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 27.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 1048
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 1049
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4.1.3 Valid Flash Module Commands Table 27-30.
PAGE 1050
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4.1.4 P-Flash Commands Table 27-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module. Table 27-31. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify PFlash Section 0x04 Read Once 0x05 Load Data Field Load data for simultaneous multiple P-Flash block operations.
PAGE 1051
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-32. D-Flash Commands FCMD Command Function on D-Flash Memory 0x08 Erase All Blocks Erase all D-Flash (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command.
PAGE 1052
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 27.4.2.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 27-33.
PAGE 1053
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-36. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if an invalid global address [22:16] is supplied FSTAT FPVIOL FERSTAT 27.4.2.
PAGE 1054
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-38. Erase Verify P-Flash Section Command Error Handling Register Error Bit FERSTAT EPVIOLIF 27.4.2.4 Error Condition None Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the Program Once command described in Section 27.4.2.7.
PAGE 1055
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-41. Load Data Field Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x05 Global address [22:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed(1) 010 Word 0 011 Word 1 100 Word 2 101 1.
PAGE 1056
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 27-43.
PAGE 1057
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 27-45.
PAGE 1058
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-47. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released.
PAGE 1059
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-50.
PAGE 1060
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4.2.11 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is successful, will release security. Table 27-53. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and D-Flash memory space and verify that it is erased.
PAGE 1061
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x7F_FF00, etc.
PAGE 1062
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-58. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0002 User Margin-0 Level(2) 1. Read margin to the erased state 2. Read margin to the programmed state Table 27-59.
PAGE 1063
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Valid margin level settings for the Set Field Margin Level command are defined in Table 27-61. Table 27-61. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level(1) 0x0002 User Margin-0 Level(2) 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1. Read margin to the erased state 2. Read margin to the programmed state Table 27-62.
PAGE 1064
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-63.
PAGE 1065
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-64.
PAGE 1066
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-66.
PAGE 1067
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-68.
PAGE 1068
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-70.
PAGE 1069
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4.2.20 Disable EEPROM Emulation Command The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE activity. Table 27-73.
PAGE 1070
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Table 27-76. EEPROM Emulation Query Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if command not available in current mode (see Table 27-30) FSTAT FERSTAT FPVIOL None MGSTAT1 None MGSTAT0 None EPVIOLIF None 27.4.2.
PAGE 1071
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) • • • Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 (see Table 27-7) Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 27-7) Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 27-7) The D-Flash user partition will start at global address 0x10_0000.
PAGE 1072
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) 27.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. Table 27-79.
PAGE 1073
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) Flash Command Interrupt Request CCIE CCIF ERSERIE ERSERIF PGMERIE PGMERIF EPVIOLIE EPVIOLIF Flash Error Interrupt Request ERSVIE1 ERSVIF1 ERSVIE0 ERSVIF0 DFDIE DFDIF SFDIE SFDIF Figure 27-27. Flash Module Interrupts Implementation 27.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 27.4.3, “Interrupts”). 27.4.
PAGE 1074
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) The security state out of reset can be permanently changed by programming the security byte of the Flash configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
PAGE 1075
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) (0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. 27.5.
PAGE 1076
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1077
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-1. Revision History Revision Number Revision Date V02.09 29 Nov 2007 V02.10 19 Dec 2007 V02.11 25 Sep 2009 Sections Affected Description of Changes - Cleanup 28.4.2/28-1113 - Updated Command Error Handling tables based on parent-child relationship with FTM1024K5 28.4.2/28-1113 - Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash, and EEPROM Emulation Query commands 28.3.
PAGE 1078
• • 32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic Flash memory primarily intended for nonvolatile data storage, or as a combination of both 4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both The Flash memory is ideal for single-supply applicati
PAGE 1079
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased. The D-Flash sector consists of four 64 byte rows for a total of 256 bytes. EEE (Emulated EEPROM) — A method to emulate the small sector size features and endurance characteristics associated with an EEPROM.
PAGE 1080
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) • Ability to program up to four words in a burst sequence 28.1.2.
PAGE 1081
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 16bit internal bus Flash Interface Command Interrupt Request Registers Error Interrupt Request Protection Security Oscillator Clock (XTAL) XGATE Clock Divider FCLK Scratch RAM 512x16 Buffer RAM 2Kx16 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127 P-Flash Block 1S 16Kx72 P-Flash Block 1N 16Kx72 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127 P-Flash Block 2 32Kx72 16Kx72 16Kx72 Memory Controller CPU P-Flash Block 0
PAGE 1082
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 28.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x74_0000 and 0x7F_FFFF as shown in Table 28-2.
PAGE 1083
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-3. Flash Configuration Field(1) Global Address Size (Bytes) 0x7F_FF0E2 1 Description Flash Nonvolatile byte Refer to Section 28.3.2.14, “Flash Option Register (FOPT)” Flash Security byte Refer to Section 28.3.2.2, “Flash Security Register (FSEC)” 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence.
PAGE 1084
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) P-Flash START = 0x74_0000 Flash Protected/Unprotected Region 736 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 28-2.
PAGE 1085
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 28.4.2.7, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 28-5.
PAGE 1086
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 1.
PAGE 1087
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) The Full Partition D-Flash command (see Section 28.4.2.15) is used to program the EEE nonvolatile information register fields where address 0x12_0000 defines the D-Flash partition for user access and address 0x12_0004 defines the buffer RAM partition for EEE operations. Table 28-7. EEE Nonvolatile Information Register Fields Global Address (EEEIFRON) Size (Bytes) 0x12_0000 – 0x12_0001 2 D-Flash User Partition (DFPART) Refer to Section 28.4.2.
PAGE 1088
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Address & Name 0x0005 FERCNFG 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C ETAGHI 0x000D ETAGLO 0x000E FECCRHI 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 7 6 ERSERIE PGMERIE R 5 4 3 2 1 0 EPVIOLIE ERSVIE1 ERSVIE0 DFDIE SFDIE MGBUSY RSVD MGSTAT1 MGSTAT0 EPVIOLIF ERSVIF1 ERSVIF0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 0 W R
PAGE 1089
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Address & Name 0x0013 FRSV2 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W = Unimplemented or Reserved Figure 28-4. FTM768K4 Register Summary (continued) 28.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIV[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 28-5.
PAGE 1090
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-9. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) MIN(1) FDIV[6:0] MAX(2) OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 33.60 34.65 0x20 67.20 68.25 0x40 1.60 2.10 0x01 34.65 35.70 0x21 68.25 69.30 0x41 2.40 3.15 0x02 35.70 36.75 0x22 69.30 70.35 0x42 3.20 4.20 0x03 36.75 37.80 0x23 70.35 71.40 0x43 4.20 5.25 0x04 37.80 38.85 0x24 71.40 72.
PAGE 1091
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 2. FDIV shown generates an FCLK frequency of 1.05 MHz 28.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 28-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 1092
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-12. Flash Security States SEC[1:0] Status of Security 00 SECURED 01 SECURED(1) 10 UNSECURED 11 SECURED 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 28.5. 28.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 1093
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-14. FECCRIX Field Descriptions Field Description 2-0 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 28.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. 28.3.2.5 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array read access from the CPU or XGATE.
PAGE 1094
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-15. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
PAGE 1095
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-16. FERCNFG Field Descriptions (continued) Field Description 3 ERSVIE1 EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error is detected during an EEE operation. 0 ERSVIF1 interrupt disabled 1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 28.3.2.
PAGE 1096
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-17. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 1097
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-18. FERSTAT Field Descriptions Field Description 7 ERSERIF EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF.
PAGE 1098
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Offset Module Base + 0x0008 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 28-13. Flash Protection Register (FPROT) The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 28.3.2.9.1, “P-Flash Protection Restrictions,” and Table 28-23).
PAGE 1099
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-20. P-Flash Protection Function Function(1) FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1. For range sizes, refer to Table 28-21 and Table 28-22. Table 28-21.
PAGE 1100
FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 FPLS[1:0] FPHDIS = 1 FPLDIS = 0 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] Scenario FLASH START FPHDIS = 1 FPLDIS = 1 FPOPEN = 1 Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 28-14.
PAGE 1101
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 28-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 28-23.
PAGE 1102
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected. Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection violation error and the EPVIOLIF flag will be set in the FERSTAT register.
PAGE 1103
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 28-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 28-17. Flash Common Command Object Low Register (FCCOBLO) 28.3.2.11.
PAGE 1104
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 28.3.2.12 EEE Tag Counter Register (ETAG) The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need to be programmed into the D-Flash EEE partition.
PAGE 1105
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults, the priority for fault recording is: 1. Double bit fault over single bit fault 2. CPU over XGATE Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 28-20.
PAGE 1106
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-28. FECCR Index=000 Bit Descriptions Field Description 15:8 PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits, allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00. 7 XBUS01 Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access from the CPU or XGATE.
PAGE 1107
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-23. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 28.3.2.16 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 1108
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4 Functional Description 28.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents or configure module resources for EEE operation.
PAGE 1109
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4.1.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 28.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 1110
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 1111
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4.1.3 Valid Flash Module Commands Table 28-30.
PAGE 1112
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4.1.4 P-Flash Commands Table 28-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module. Table 28-31. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify PFlash Section 0x04 Read Once 0x05 Load Data Field Load data for simultaneous multiple P-Flash block operations.
PAGE 1113
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-32. D-Flash Commands FCMD Command Function on D-Flash Memory 0x08 Erase All Blocks Erase all D-Flash (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command.
PAGE 1114
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 28.4.2.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 28-33.
PAGE 1115
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-36. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if an invalid global address [22:16] is supplied(1) FSTAT FPVIOL None MGSTAT1 Set if any errors have been encountered during the read(2) MGSTAT0 Set if any non-correctable errors have been encountered during the read2 FERSTAT EPVIOLIF None 1.
PAGE 1116
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-38.
PAGE 1117
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-40. Read Once Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if a Load Data Field command sequence is currently active ACCERR Set if command not available in current mode (see Table 28-30) FSTAT Set if an invalid phrase index is supplied FPVIOL FERSTAT 28.4.2.
PAGE 1118
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-42.
PAGE 1119
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-44.
PAGE 1120
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) values for the Program Once command range from 0x0000 to 0x0007. During execution of the Program Once command, any attempt to read addresses within P-Flash block 0 will return invalid data. Table 28-46.
PAGE 1121
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-48.
PAGE 1122
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4.2.10 Erase P-Flash Sector Command The Erase P-Flash Sector operation will erase all addresses in a P-Flash sector. Table 28-51. Erase P-Flash Sector Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x0A Global address [22:16] to identify P-Flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Section 28.1.2.1 for the P-Flash sector size.
PAGE 1123
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) state. During the execution of this command (CCIF=0) the user must not write to any Flash module register. The CCIF flag is set after the Unsecure Flash operation has completed. Table 28-54.
PAGE 1124
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-56. Verify Backdoor Access Key Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 100 at command launch Set if a Load Data Field command sequence is currently active ACCERR Set if an incorrect backdoor key is supplied Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see Section 28.3.2.
PAGE 1125
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-59. Set User Margin Level Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 001 at command launch Set if a Load Data Field command sequence is currently active ACCERR Set if command not available in current mode (see Table 28-30) Set if an invalid global address [22:16] is supplied(1) FSTAT Set if an invalid margin level setting is supplied FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None 1.
PAGE 1126
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-61. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0002 User Margin-0 Level(2) 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1. Read margin to the erased state 2. Read margin to the programmed state Table 28-62.
PAGE 1127
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-63.
PAGE 1128
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-64.
PAGE 1129
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-66.
PAGE 1130
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-68.
PAGE 1131
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-70.
PAGE 1132
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4.2.20 Disable EEPROM Emulation Command The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE activity. Table 28-73.
PAGE 1133
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Table 28-76. EEPROM Emulation Query Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if command not available in current mode (see Table 28-30) FSTAT FERSTAT FPVIOL None MGSTAT1 None MGSTAT0 None EPVIOLIF None 28.4.2.
PAGE 1134
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) • • • Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 (see Table 28-7) Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 28-7) Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 28-7) The D-Flash user partition will start at global address 0x10_0000.
PAGE 1135
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) 28.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. Table 28-79.
PAGE 1136
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) Flash Command Interrupt Request CCIE CCIF ERSERIE ERSERIF PGMERIE PGMERIF EPVIOLIE EPVIOLIF Flash Error Interrupt Request ERSVIE1 ERSVIF1 ERSVIE0 ERSVIF0 DFDIE DFDIF SFDIE SFDIF Figure 28-27. Flash Module Interrupts Implementation 28.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 28.4.3, “Interrupts”). 28.4.
PAGE 1137
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) The security state out of reset can be permanently changed by programming the security byte of the Flash configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
PAGE 1138
Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) (0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. 28.5.
PAGE 1139
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-1. Revision History Revision Number Revision Date Sections Affected V02.08 14 Nov 2007 29.5.2/29-1200 - Changed terminology from ‘word program’ to “Program P-Flash’ in the BDM unsecuring description, Section 29.5.2 29.4.2/29-1176 - Added requirement that user not write any Flash module register during execution of commands ‘Erase All Blocks’, Section 29.4.2.8, and ‘Unsecure Flash’, Section 29.4.2.
PAGE 1140
29.
PAGE 1141
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store required for EEE. Memory space in the D-Flash memory not required for EEE can be partitioned to provide nonvolatile memory space for applications.
PAGE 1142
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.1.2.2 • • • • • • Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access Dedicated commands to control access to the D-Flash memory over EEE operation Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Ability to program up to four words in a burst sequence 29.
PAGE 1143
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 16bit internal bus Flash Interface Command Interrupt Request Registers Error Interrupt Request Protection Security Oscillator Clock (XTAL) XGATE Clock Divider FCLK Memory Controller CPU Scratch RAM 512x16 Buffer RAM 2Kx16 D-Flash 16Kx22 P-Flash Block 0 32Kx72 16Kx72 16Kx72 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127 P-Flash Block 1S 16Kx72 P-Flash Block 1N 16Kx72 sector 0 sector 1 sector 0 sector 1 sector 127 sector 127
PAGE 1144
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.3 Memory Map and Registers This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. 29.3.1 Module Memory Map The S12X architecture places the P-Flash memory between global addresses 0x70_0000 and 0x7F_FFFF as shown in Table 29-2.
PAGE 1145
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-3. Flash Configuration Field(1) Global Address Size (Bytes) 0x7F_FF0E2 1 Description Flash Nonvolatile byte Refer to Section 29.3.2.14, “Flash Option Register (FOPT)” Flash Security byte Refer to Section 29.3.2.2, “Flash Security Register (FSEC)” 1. Older versions may have swapped protection byte addresses 2. 0x7FF08 - 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence.
PAGE 1146
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) P-Flash START = 0x70_0000 Flash Protected/Unprotected Region 992 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 P-Flash END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 29-2.
PAGE 1147
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-4. Program IFR Fields Global Address (PGMIFRON) Size (Bytes) 0x40_0000 – 0x40_0007 8 Device ID 0x40_0008 – 0x40_00E7 224 Reserved 0x40_00E8 – 0x40_00E9 2 Version ID 0x40_00EA – 0x40_00FF 22 Reserved 0x40_0100 – 0x40_013F 64 Program Once Field Refer to Section 29.4.2.7, “Program Once Command” 0x40_0140 – 0x40_01FF 192 Reserved Field Description Table 29-5.
PAGE 1148
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-6.
PAGE 1149
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) D-Flash START = 0x10_0000 D-Flash User Partition D-Flash Memory 32 Kbytes D-Flash EEE Partition D-Flash END = 0x10_7FFF 0x12_0000 0x12_1000 0x12_2000 0x12_4000 EEE Nonvolatile Information Register (EEEIFRON) 128 bytes EEE Tag RAM (TMGRAMON) 256 bytes Memory Controller Scratch RAM (TMGRAMON) 1024 bytes 0x12_E000 0x12_FFFF Buffer RAM START = 0x13_F000 Buffer RAM User Partition 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_
PAGE 1150
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-7. EEE Nonvolatile Information Register Fields Global Address (EEEIFRON) Size (Bytes) 0x12_0000 – 0x12_0001 2 D-Flash User Partition (DFPART) Refer to Section 29.4.2.15, “Full Partition D-Flash Command” 0x12_0002 – 0x12_0003 2 D-Flash User Partition (duplicate(1)) 0x12_0004 – 0x12_0005 2 Buffer RAM EEE Partition (ERPART) Refer to Section 29.4.2.
PAGE 1151
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Address & Name 0x0006 FSTAT 0x0007 FERSTAT 0x0008 FPROT 0x0009 EPROT 0x000A FCCOBHI 0x000B FCCOBLO 0x000C ETAGHI 0x000D ETAGLO 0x000E FECCRHI 0x000F FECCRLO 0x0010 FOPT 0x0011 FRSV0 0x0012 FRSV1 0x0013 FRSV2 7 6 R 5 4 3 2 1 0 ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 EPVIOLIF ERSVIF1 ERSVIF0 DFDIF SFDIF FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 RNV5 RNV4 EPDIS EPS2 EPS1 EPS0 0 CCIF W R 0 ERSERIF PGMERIF W R RNV6 FPOPEN W
PAGE 1152
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Address & Name 7 6 5 4 3 2 1 0 = Unimplemented or Reserved Figure 29-4. FTM1024K5 Register Summary (continued) 29.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. Offset Module Base + 0x0000 7 R 6 5 4 3 2 1 0 0 0 0 FDIVLD FDIV[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 29-5.
PAGE 1153
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-9. FDIV vs OSCCLK Frequency OSCCLK Frequency (MHz) MIN(1) FDIV[6:0] MAX(2) OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 OSCCLK Frequency (MHz) MIN 1 MAX FDIV[6:0] 2 33.60 34.65 0x20 67.20 68.25 0x40 1.60 2.10 0x01 34.65 35.70 0x21 68.25 69.30 0x41 2.40 3.15 0x02 35.70 36.75 0x22 69.30 70.35 0x42 3.20 4.20 0x03 36.75 37.80 0x23 70.35 71.40 0x43 4.20 5.25 0x04 37.80 38.85 0x24 71.40 72.
PAGE 1154
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 2. FDIV shown generates an FCLK frequency of 1.05 MHz 29.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. Offset Module Base + 0x0001 7 R 6 5 4 KEYEN[1:0] 3 2 1 RNV[5:2] 0 SEC[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 29-6. Flash Security Register (FSEC) All bits in the FSEC register are readable but not writable.
PAGE 1155
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-12. Flash Security States SEC[1:0] Status of Security 00 SECURED 01 SECURED(1) 10 UNSECURED 11 SECURED 1. Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 29.5. 29.3.2.3 Flash CCOB Index Register (FCCOBIX) The FCCOBIX register is used to index the FCCOB register for Flash memory operations.
PAGE 1156
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-14. FECCRIX Field Descriptions Field Description 2-0 ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is ECCRIX[2:0] being read. See Section 29.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details. 29.3.2.
PAGE 1157
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-15. FCNFG Field Descriptions (continued) Field Description 1 FDFD Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD. The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is detected.
PAGE 1158
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-16. FERCNFG Field Descriptions (continued) Field Description 3 ERSVIE1 EEE Error Type 1 Interrupt Enable — The ERSVIE1 bit controls interrupt generation when a change state error is detected during an EEE operation. 0 ERSVIF1 interrupt disabled 1 An interrupt will be requested whenever the ERSVIF1 flag is set (see Section 29.3.2.
PAGE 1159
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-17. FSTAT Field Descriptions Field Description 7 CCIF Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
PAGE 1160
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-18. FERSTAT Field Descriptions Field Description 7 ERSERIF EEE Erase Error Interrupt Flag — The setting of the ERSERIF flag occurs due to an error in a Flash erase command that resulted in the erase operation not being successful during EEE operations. The ERSERIF flag is cleared by writing a 1 to ERSERIF. Writing a 0 to the ERSERIF flag has no effect on ERSERIF.
PAGE 1161
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Offset Module Base + 0x0008 7 6 R 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS[1:0] FPLDIS FPLS[1:0] W Reset F F F F F F F F = Unimplemented or Reserved Figure 29-13. Flash Protection Register (FPROT) The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Section 29.3.2.9.1, “P-Flash Protection Restrictions,” and Table 29-23).
PAGE 1162
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-20. P-Flash Protection Function Function(1) FPOPEN FPHDIS FPLDIS 1 1 1 No P-Flash Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full P-Flash Memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1. For range sizes, refer to Table 29-21 and Table 29-22. Table 29-21.
PAGE 1163
FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 7 6 5 4 3 2 1 0 Scenario 0x7F_8000 0x7F_FFFF Scenario FPHS[1:0] FPLS[1:0] FLASH START FPOPEN = 1 Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) FPHS[1:0] 0x7F_8000 FPOPEN = 0 FPLS[1:0] FLASH START 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 29-14.
PAGE 1164
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.3.2.9.1 P-Flash Protection Restrictions The general guideline is that P-Flash protection can only be added and not removed. Table 29-23 specifies all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS bit descriptions for additional restrictions. Table 29-23.
PAGE 1165
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) containing the EEE protection byte during the reset sequence, the EPOPEN bit will be cleared and remaining bits in the EPROT register will be set to leave the buffer RAM EEE partition fully protected. Trying to write data to any protected area in the buffer RAM EEE partition will result in a protection violation error and the EPVIOLIF flag will be set in the FERSTAT register.
PAGE 1166
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Offset Module Base + 0x000A 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[15:8] W Reset 0 0 0 0 Figure 29-16. Flash Common Command Object High Register (FCCOBHI) Offset Module Base + 0x000B 7 6 5 4 3 2 1 0 0 0 0 0 R CCOB[7:0] W Reset 0 0 0 0 Figure 29-17. Flash Common Command Object Low Register (FCCOBLO) 29.3.2.11.
PAGE 1167
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-26. FCCOB - NVM Command Mode (Typical Usage) CCOBIX[2:0] Byte FCCOB Parameter Fields (NVM Command Mode) HI Data 1 [15:8] LO Data 1 [7:0] HI Data 2 [15:8] LO Data 2 [7:0] HI Data 3 [15:8] LO Data 3 [7:0] 011 100 101 29.3.2.12 EEE Tag Counter Register (ETAG) The ETAG register contains the number of outstanding words in the buffer RAM EEE partition that need to be programmed into the D-Flash EEE partition.
PAGE 1168
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) fault information will be recorded until the specific ECC fault flag has been cleared. In the event of simultaneous ECC faults, the priority for fault recording is: 1. Double bit fault over single bit fault 2. CPU over XGATE Offset Module Base + 0x000E 7 6 5 4 R 3 2 1 0 0 0 0 0 ECCR[15:8] W Reset 0 0 0 0 = Unimplemented or Reserved Figure 29-20.
PAGE 1169
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-28. FECCR Index=000 Bit Descriptions Field Description 15:8 PAR[7:0] ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits, allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00. 7 XBUS01 Bus Source Identifier — The XBUS01 bit determines whether the ECC error was caused by a read access from the CPU or XGATE.
PAGE 1170
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Offset Module Base + 0x0011 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-23. Flash Reserved0 Register (FRSV0) All bits in the FRSV0 register read 0 and are not writable. 29.3.2.16 Flash Reserved1 Register (FRSV1) This Flash register is reserved for factory testing.
PAGE 1171
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4 Functional Description 29.4.1 Flash Command Operations Flash command operations are used to modify Flash memory contents or configure module resources for EEE operation.
PAGE 1172
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4.1.2.1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register (see Section 29.3.2.3). The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0).
PAGE 1173
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) START Read: FCLKDIV register Clock Register Written Check no FDIVLD Set? yes Write: FCLKDIV register Note: FCLKDIV must be set after each reset Read: FSTAT register FCCOB Availability Check CCIF Set? no Results from previous Command yes Access Error and Protection Violation Check ACCERR/ FPVIOL Set? no yes Write: FSTAT register Clear ACCERR/FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load.
PAGE 1174
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4.1.3 Valid Flash Module Commands Table 29-30.
PAGE 1175
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4.1.4 P-Flash Commands Table 29-31 summarizes the valid P-Flash commands along with the effects of the commands on the PFlash block and other resources within the Flash module. Table 29-31. P-Flash Commands FCMD Command 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify PFlash Section 0x04 Read Once 0x05 Load Data Field Load data for simultaneous multiple P-Flash block operations.
PAGE 1176
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-32. D-Flash Commands FCMD Command Function on D-Flash Memory 0x08 Erase All Blocks Erase all D-Flash (and P-Flash) blocks. An erase of all Flash blocks is only possible when the FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command.
PAGE 1177
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. 29.4.2.1 Erase Verify All Blocks Command The Erase Verify All Blocks command will verify that all P-Flash and D-Flash blocks have been erased. Table 29-33.
PAGE 1178
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-36. Erase Verify Block Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if an invalid global address [22:16] is supplied FSTAT FPVIOL FERSTAT 29.4.2.
PAGE 1179
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-38. Erase Verify P-Flash Section Command Error Handling Register Error Bit FERSTAT EPVIOLIF 29.4.2.4 Error Condition None Read Once Command The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash block 0. The Read Once field is programmed using the Program Once command described in Section 29.4.2.7.
PAGE 1180
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-41. Load Data Field Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x05 Global address [22:16] to identify P-Flash block 001 Global address [15:0] of phrase location to be programmed(1) 010 Word 0 011 Word 1 100 Word 2 101 1.
PAGE 1181
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) CAUTION A P-Flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash phrase is not allowed. Table 29-43.
PAGE 1182
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 29-45.
PAGE 1183
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-47. Erase All Blocks Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x08 Not required Upon clearing CCIF to launch the Erase All Blocks command, the Memory Controller will erase the entire Flash memory space and verify that it is erased. If the Memory Controller verifies that the entire Flash memory space was properly erased, security will be released.
PAGE 1184
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-50.
PAGE 1185
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4.2.11 Unsecure Flash Command The Unsecure Flash command will erase the entire P-Flash and D-Flash memory space and, if the erase is successful, will release security. Table 29-53. Unsecure Flash Command FCCOB Requirements CCOBIX[2:0] 000 FCCOB Parameters 0x0B Not required Upon clearing CCIF to launch the Unsecure Flash command, the Memory Controller will erase the entire P-Flash and D-Flash memory space and verify that it is erased.
PAGE 1186
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Upon clearing CCIF to launch the Verify Backdoor Access Key command, the Memory Controller will check the FSEC KEYEN bits to verify that this command is enabled. If not enabled, the Memory Controller sets the ACCERR bit in the FSTAT register and terminates. If the command is enabled, the Memory Controller compares the key provided in FCCOB to the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x7F_FF00, etc.
PAGE 1187
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-58. Valid Set User Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0002 User Margin-0 Level(2) 1. Read margin to the erased state 2. Read margin to the programmed state Table 29-59.
PAGE 1188
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Valid margin level settings for the Set Field Margin Level command are defined in Table 29-61. Table 29-61. Valid Set Field Margin Level Settings CCOB (CCOBIX=001) Level Description 0x0000 Return to Normal Level 0x0001 User Margin-1 Level(1) 0x0002 User Margin-0 Level(2) 0x0003 Field Margin-1 Level1 0x0004 Field Margin-0 Level2 1. Read margin to the erased state 2. Read margin to the programmed state Table 29-62.
PAGE 1189
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-63.
PAGE 1190
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-64.
PAGE 1191
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-66.
PAGE 1192
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-68.
PAGE 1193
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-70.
PAGE 1194
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4.2.20 Disable EEPROM Emulation Command The Disable EEPROM Emulation command causes the Memory Controller to suspend current EEE activity. Table 29-73.
PAGE 1195
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Table 29-76. EEPROM Emulation Query Command Error Handling Register Error Bit Error Condition Set if CCOBIX[2:0] != 000 at command launch ACCERR Set if a Load Data Field command sequence is currently active Set if command not available in current mode (see Table 29-30) FSTAT FERSTAT FPVIOL None MGSTAT1 None MGSTAT0 None EPVIOLIF None 29.4.2.
PAGE 1196
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) • • • Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 (see Table 29-7) Program ERPART to the EEE nonvolatile information register at global address 0x12_0004 (see Table 29-7) Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 (see Table 29-7) The D-Flash user partition will start at global address 0x10_0000.
PAGE 1197
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) 29.4.3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault. Table 29-79.
PAGE 1198
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) Flash Command Interrupt Request CCIE CCIF ERSERIE ERSERIF PGMERIE PGMERIF EPVIOLIE EPVIOLIF Flash Error Interrupt Request ERSVIE1 ERSVIF1 ERSVIE0 ERSVIF0 DFDIE DFDIF SFDIE SFDIF Figure 29-27. Flash Module Interrupts Implementation 29.4.4 Wait Mode The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU from wait via the CCIF interrupt (see Section 29.4.3, “Interrupts”). 29.4.
PAGE 1199
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) The security state out of reset can be permanently changed by programming the security byte of the Flash configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and program commands are available and that the upper region of the P-Flash is unprotected. If the Flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
PAGE 1200
Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) (0x7F_FF0F). The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the Flash protection register, FPROT. 29.5.
PAGE 1201
Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General NOTE The electrical characteristics given in this section should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. This supplement contains the most accurate electrical information for the MC9S12XE-Family microcontroller available at the time of publication.
PAGE 1202
Appendix A Electrical Characteristics NOTE Connecting VDDR to VSS disables the internal voltage regulator. The VDDF, VSS1 pin pair supplies the internal NVM logic. The VDD, VSS2 are the supply pins for the internal digital logic. VDDPLL, VSSPLL pin pair supply the oscillator and the PLL. VSS1, VSS2 and VSS3 are internally connected by metal. VDDA1, and VDDA2 are internally connected by metal. All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal.
PAGE 1203
Appendix A Electrical Characteristics A.1.3.3 Oscillator The pins EXTAL, XTAL dedicated to the oscillator have a nominal 1.8 V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.4 Current Injection Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and operating maximum current conditions.
PAGE 1204
Appendix A Electrical Characteristics maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35). Table A-1. Absolute Maximum Ratings(1) Num Rating 1 I/O, regulator and analog supply voltage 2 Digital logic supply voltage(2) 3 Symbol Min Max Unit VDD35 –0.3 6.0 V VDD –0.3 2.16 V VDDPLL –0.3 2.16 V 2 PLL supply voltage 2 4 NVM supply voltage VDDF –0.
PAGE 1205
Appendix A Electrical Characteristics specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Series resistance R1 1500 Ohm Storage capacitance C 100 pF Number of pulse per pin Positive Negative — — 1 1 Charged Device Number of pulse per pin Positive Negative — — 3 3 Human Body Latch-up Minimum input voltage limit –2.
PAGE 1206
Appendix A Electrical Characteristics A.1.7 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4.
PAGE 1207
Appendix A Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.
PAGE 1208
Appendix A Electrical Characteristics Table A-5.
PAGE 1209
Appendix A Electrical Characteristics Table A-6.
PAGE 1210
Appendix A Electrical Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins. s Table A-7. 3.3-V I/O Characteristics Conditions are 3.13 V < VDD35 < 3.6 V temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C 1 Rating Symbol Min Typ Max Unit P Input high voltage VIH 0.65*VDD35 — — T Input high voltage VIH — — VDD35 + 0.
PAGE 1211
Appendix A Electrical Characteristics Table A-7. 3.3-V I/O Characteristics Conditions are 3.13 V < VDD35 < 3.6 V temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins.
PAGE 1212
Appendix A Electrical Characteristics Table A-8. 5V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. Num C Rating Symbol Min 1 P Input high voltage VIH T Input high voltage Max Unit 0.65*VDD35 — — V VIH — — VDD35 + 0.3 V P Input low voltage VIL — — 0.35*VDD35 V T Input low voltage VIL VSS35 – 0.
PAGE 1213
Appendix A Electrical Characteristics Table A-8. 5V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V temperature from –40°C to +150°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,TEST and supply pins. 16 D Port H, J, P interrupt input pulse passed (STOP) tPULSE 4 — — tcyc 17 D IRQ pulse width, edge-sensitive mode (STOP) PWIRQ 1 — — tcyc 4 — — tosc PWXIRQ 18 D XIRQ pulse width with X-bit set (STOP) 1.
PAGE 1214
Appendix A Electrical Characteristics Table A-9. Characteristics of Expantion Bus Inputs Port C, D, PE5, PE6, and PE7 for Reduced Input Voltage Thresholds Conditions are 4.5 V < VDD35 < 5.5 V Temperature from –40°C to +150°C, unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D Input high voltage VIH 1.75 — — V 2 D Input low voltage VIL — — 0.75 V 3 T Input hysteresis VHYS — 100 — mV A.1.
PAGE 1215
Appendix A Electrical Characteristics Table A-10.
PAGE 1216
Appendix A Electrical Characteristics Table A-12. Module Run Supply Currents Conditions are shown in Table A-10 at ambient temperature unless otherwise noted Num C Rating Min Typ Max Unit 1 T S12XCPU — 12.76 — mA 2 T XGATE — 24.20 — 3 T Each MSCAN — 1.05 — 4 T Each SPI — 0.22 — 5 T Each SCI — 0.28 — 6 T Each IIC — 0.40 — 7 T PWM — 0.55 — 8 T ECT — 1.16 — 9 T Each ATD — 0.82 — 10 T PIT — 0.61 — 11 T RTI — 0.
PAGE 1217
Appendix A Electrical Characteristics Table A-13. Run and Wait Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 100 mA Run supply current (No external load, Peripheral Configuration see Table A-11.) 1 P Peripheral Set1 fosc=4MHz, fbus=50MHz IDD35 — — Run supply current (No external load, Peripheral Configuration see Table A-10.
PAGE 1218
Appendix A Electrical Characteristics Table A-14.
PAGE 1219
Appendix A Electrical Characteristics A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics The Table A-15 and Table A-16 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to.
PAGE 1220
Appendix A Electrical Characteristics A.2.2.2 Port AD Output Drivers Switching PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply pins. Although internal design measures are implemented to minimize the affect of output driver noise, it is recommended to configure PortAD pins as outputs only for low frequency, low load outputs.
PAGE 1221
Appendix A Electrical Characteristics The additional input voltage error on the converted channel can be calculated as: VERR = K * RS * IINJ with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-16.
PAGE 1222
Appendix A Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $FF $3FC $3FB $3FA $3F9 $FE $3F8 $3F7 $3F6 $3F5 10-Bit Resolution $3F3 9 Ideal Transfer Curve 2 8 8-Bit Resolution $FD $3F4 7 10-Bit Transfer Curve 6 5 1 4 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 50 50555060506550705075508050855090509551005105511051155120 Vin mV Figure A-1.
PAGE 1223
Appendix A Electrical Characteristics Table A-17. ATD Conversion Performance 5V range Conditions are shown in Table A-4. unless otherwise noted. VREF = VRH - VRL = 5.12V. fATDCLK = 8.3MHz The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions. Rating(1) ,(2) Num C Symbol Min Typ Max Unit 1 P Resolution 12-Bit LSB — 1.25 — mV 2 P Differential Nonlinearity 12-Bit DNL -4 ±2 4 counts 3 P Integral Nonlinearity 12-Bit INL -5 ±2.
PAGE 1224
Appendix A Electrical Characteristics A.3 A.3.1 NVM, Flash and Emulated EEPROM Timing Parameters The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum.
PAGE 1225
Appendix A Electrical Characteristics A.3.1.4 Read Once (FCMD=0x04) The maximum read once time is given by 1 t = ( 400 ) ⋅ ---------------------f NVMBUS A.3.1.5 Load Data Field (FCMD=0x05) The maximum load data field time is given by 1 t = ( 450 ) ⋅ ---------------------f NVMBUS A.3.1.
PAGE 1226
Appendix A Electrical Characteristics A.3.1.9 Erase P-Flash Block (FCMD=0x09) Erasing a 256K NVM block takes 1 1 t mass ≈ 100100 ⋅ ------------------------- + 70000 ⋅ ----------------------------f NVMBUS f NVMOP Erasing a 128K NVM block takes 1 1 t mass ≈ 100100 ⋅ ------------------------- + 35000 ⋅ ----------------------------f NVMBUS f NVMOP A.3.1.
PAGE 1227
Appendix A Electrical Characteristics 1 t = 350 ⋅ ----------------------------f NVMBUS A.3.1.15 Full Partition D-Flash (FCMD=0x0F) The maximum time for partitioning the D-flash (ERPART=16, DFPART=0) is given by : 1 1 t part ≈ 21800 ⋅ ------------------------- + 400000 ⋅ ----------------------------- + t f NVMOP f NVMBUS mass A.3.1.16 Erase Verify D-Flash Section (FCMD=0x10) Erase Verify D-Flash for a given number of words NW is given by .
PAGE 1228
Appendix A Electrical Characteristics A.3.1.19 Enable EEE (FCMD=0x13) The maximum time to enable EPROM emulation is given by 1 t = ⎛ ⎛ ( ( 1100 ⋅ BWN + ( 176 ⋅ ( 1 + BWN ) + ( BWN + N SEC ) ⋅ 32364 ) ) ) ⋅ -------------------⎞ + ⎝⎝ f NVMOP⎠ 1 ⎛ ( 3050 ⋅ ( 1 + BWN ) + ( N -⎞ ⎞ SEC + BWN ) ⋅ 290500 ) ⋅ --------------------⎝ f NVMBUS⎠ ⎠ where NSEC is the number of sectors of constant data. A constant sector is one in which all 63 records contain the latest active data and would need to be copied.
PAGE 1229
Appendix A Electrical Characteristics A.3.1.20 Maximum CCOB Latency The maximum time a CCOB command has to wait to be actioned due to an EEE clean up is given where BWN = 1 if a brownout has occured otherwise BWN = 0. BWN = 1 only for the first ENEEE after reset. 1 1 t ≈ ⎛ 32364 ⋅ ------------------------- + 292600 ⋅ -----------------------------⎞ ⋅ ( 1 + BWN ) ⎝ f NVMBUS⎠ f NVMOP 1100 1 + BWN ⋅ ⎛ 350 ⋅ --------------------- + -------------------------⎞ ⎝ f NVMOP f NVMBUS⎠ A.3.1.
PAGE 1230
Appendix A Electrical Characteristics A.3.1.
PAGE 1231
Appendix A Electrical Characteristics 5. Maximum partitioning A.3.2 NVM Reliability Parameters The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The data retention and program/erase cycling failure rates are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. MC9S12XE-Family Reference Manual Rev.
PAGE 1232
Appendix A Electrical Characteristics The standard shipping condition for both the D-Flash and P-Flash memory is erased with security disabled. However it is recommended that each block or sector is erased before factory programming to ensure that the full data retention capability is achieved. Data retention time is measured from the last erase operation. Table A-20.
PAGE 1233
Appendix A Electrical Characteristics 5. This represents the number of writes of updated data words to the EEE_RAM partition. Typical endurance performance for the Emulated EEPROM array is based on typical endurance performance and the EEE algorithm implemented on this product family. Spec. table quotes typical endurance evaluated at 25°C for this product family. 6.
PAGE 1234
Appendix A Electrical Characteristics A.4 Voltage Regulator Device functionality is guaranteed on power down to the LVR assert level. Table A-21. Voltage Regulator Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Symbol Min Typical Max Unit 1 P Input Voltages VVDDR,A 3.13 — 5.5 V P Output Voltage Core Full Performance Mode Reduced Power Mode (MCU STOP mode) Shutdown Mode VDD 1.72 — — 1.84 1.6 —(1) 1.
PAGE 1235
Appendix A Electrical Characteristics A.5 Output Loads A.5.1 Resistive Loads The voltage regulator is intended to supply the internal logic and oscillator. It allows no external DC loads. A.5.2 Capacitive Loads The capacitive loads are specified in Table A-22. Ceramic capacitors with X7R dielectricum are required. Table A-22.
PAGE 1236
Appendix A Electrical Characteristics Figure A-4. MC9S12XE-Family Power Sequencing V VDDR, VDDX VDDA t >= 0 During power sequencing VDDA can be powered up before VDDR, VDDX. VDDR and VDDX must be powered up together adhering to the operating conditions differential. VRH power up must follow VDDA to avoid current injection. A.6 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (PLL). A.6.
PAGE 1237
Appendix A Electrical Characteristics A.6.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD35 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG flags register has not been set. A.6.1.
PAGE 1238
Appendix A Electrical Characteristics A.6.2 Oscillator Table A-24. Oscillator Characteristics Conditions are shown in Table A-4. unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1a C Crystal oscillator range (loop controlled Pierce) fOSC 4.0 — 16 MHz 1b C Crystal oscillator range (full swing Pierce) (1),(2) fOSC 2.
PAGE 1239
Appendix A Electrical Characteristics A.6.3 Phase Locked Loop A.6.3.1 Jitter Information With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter.
PAGE 1240
Appendix A Electrical Characteristics Defining the jitter as: t (N) t (N) ⎞ ⎛ max min J ( N ) = max ⎜ 1 – ----------------------- , 1 – ----------------------- ⎟ N⋅t N⋅t ⎝ nom nom ⎠ The following equation is a good fit for the maximum jitter: j1 J ( N ) = -------- + j 2 N J(N) 1 5 10 20 N Figure A-6. Maximum bus clock jitter approximation MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1241
Appendix A Electrical Characteristics This is important to note with respect to timers, serial modules where a prescaler will eliminate the effect of the jitter to a large extent. Table A-25. IPLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Self Clock Mode frequency(1) fSCM 1 — 4 MHz 2 C VCO locking range fVCO 32 — 120 MHz 3 C Reference Clock fREF 1 — 40 MHz 4 D Lock Detection |∆Lock| 0 — 1.
PAGE 1242
Appendix A Electrical Characteristics Table A-27. Measurement Conditions Description Drive mode Load capacitance CLOAD(1), on all outputs Thresholds for delay measurement points 1. Timing specified for equal load on all SPI output pins. Avoid asymmetric load. A.7.2.1 Value Unit Full drive mode — 50 pF (20% / 80%) VDDX V Master Mode In Figure A-7 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
PAGE 1243
Appendix A Electrical Characteristics In Figure A-8 the timing diagram for master mode with transmission format CPHA=1 is depicted. SS1 (Output) 1 2 12 13 12 13 3 SCK (CPOL = 0) (Output) 4 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 6 MSB IN2 Port Data LSB IN 11 9 MOSI (Output) Bit MSB-1. . . 1 Master MSB OUT2 Bit MSB-1. . . 1 Master LSB OUT Port Data 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB. Figure A-8.
PAGE 1244
Appendix A Electrical Characteristics In Table A-28 the timing characteristics for master mode are listed. Table A-28.
PAGE 1245
Appendix A Electrical Characteristics A.7.2.2 Slave Mode In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 0 is depicted. SS (Input) 1 12 13 3 12 13 SCK (CPOL = 0) (Input) 4 2 4 SCK (CPOL = 1) (Input) 10 8 7 MISO (Output) 9 See Note Slave MSB 5 MOSI (Input) 11 11 Bit MSB-1 . . . 1 Slave LSB OUT See Note 6 Bit MSB-1. . . 1 MSB IN LSB IN NOTE: Not defined Figure A-10.
PAGE 1246
Appendix A Electrical Characteristics In Table A-29 the timing characteristics for slave mode are listed. Table A-29.
PAGE 1247
Appendix A Electrical Characteristics A.7.3 External Bus Timing The following conditions are assumed for all following external bus timing values: • Crystal input within 45% to 55% duty • Equal 25 pF load on all pins • Pad full drive (reduced drive must be off) A.7.3.1 Normal Expanded Mode (External Wait Feature Disabled) 1 1 CSx ADDRx ADDR1 2 ADDR2 3 RE 4 5 WE 8 6 7 10 DATAx (Read) DATA1 11 (Write) DATA2 9 EWAIT UDS, LDS Figure A-12.
PAGE 1248
Appendix A Electrical Characteristics Table A-30. Example 1a: Normal Expanded Mode Timing 50 MHz bus (EWAIT disabled) No. - Characteristic Frequency of internal bus - Internal cycle time - Frequency of external bus VDD5=5.0V Symbol VDD5=3.3V Unit C Min Max C Min Max fi - D.C. 50.0 - D.C. 25.0 tcyc - 20 ∞ - 40 ∞ ns fo - D.C. 25.0 - D.C. 12.
PAGE 1249
Appendix A Electrical Characteristics A.7.3.2 Normal Expanded Mode (External Wait Feature Enabled) 1 CSx ADDRx ADDR1 2 ADDR2 3 RE WE 8 6 7 (Read) DATA1 DATAx 12 13 EWAIT UDS, LDS Figure A-13. Example 1b: Normal Expanded Mode — Stretched Read Access MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1250
Appendix A Electrical Characteristics 1 CSx ADDRx ADDR1 ADDR2 RE 4 5 WE 9 11 10 DATAx (Write) DATA1 12 13 EWAIT UDS, LDS Figure A-14. Example 1b: Normal Expanded Mode — Stretched Write Access Table A-31. Example 1b: Normal Expanded Mode Timing at 50MHz bus (EWAIT enabled) VDD5 = 5.0V No. Characteristic Symbol C - Frequency of internal bus - Internal cycle time - Frequency of external bus 2 stretch cycles VDD5 = 3.
PAGE 1251
Appendix A Electrical Characteristics Table A-31. Example 1b: Normal Expanded Mode Timing at 50MHz bus (EWAIT enabled) VDD5 = 5.0V No. Characteristic Symbol C 2 stretch cycles VDD5 = 3.
PAGE 1252
Appendix A Electrical Characteristics A.7.3.3 Emulation Single-Chip Mode (Without Wait States) 1 1 2 3 ECLK2X ECLK 5 4 7 6 ADDR [22:20]/ ACC [2:0] addr1 acc1 addr2 acc2 addr3 ADDR [19:16]/ IQSTAT [3:0] addr1 iqstat0 addr2 iqstat1 addr3 ADDR [15:0]/ IVD [15:0] addr1 ivd0 addr2 ivd1 addr3 8 9 DATAx data0 (read) data1 (write) data2 10 12 11 12 R/W LSTRB Figure A-15. Example 2a: Emulation Single-Chip Mode — Read Followed by Write MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1253
Appendix A Electrical Characteristics Table A-32. Example 2a: Emulation Single-Chip Mode Timing 50 Mhz bus, VDD5=5.0V (EWAIT disabled) Characteristic (1) No. C - - Frequency of internal bus 1 - Cycle time Symbol Min Max Unit fi D.C. 50.0 MHz tcyc 20 ∞ ns 2 D Pulse width, E high PWEH 9 - ns 3 D Pulse width, E low PWEL 9 - ns 4 D Address delay time tAD - 5 ns 5 D Address hold time tAH 0 - ns 6 D IVDx delay time (2) tIVDD - 4.
PAGE 1254
Appendix A Electrical Characteristics A.7.3.4 Emulation Expanded Mode (With Optional Access Stretching) 1 2 3 ECLK2X ECLK 5 4 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ADDR [19:16]/ IQSTAT [3:0] ADDR1 ADDR [15:0]/ IVD [15:0] ADDR1 ACC1 IQSTAT0 ? ADDR1 ADDR1 ADDR1 000 IQSTAT1 ADDR2 ADDR2 IVD1 ADDR2 8 9 DATAx DATA0 (Read) DATA1 12 12 R/W LSTRB Figure A-16. Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1255
Appendix A Electrical Characteristics 1 2 3 ECLK2X ECLK 4 5 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ACC1 ADDR1 ADDR [19:16]/ IQSTAT [3:0] ADDR1 IQSTAT0 ADDR1 ADDR [15:0]/ IVD [15:0] ADDR1 ? ADDR1 000 IQSTAT1 x ADDR2 ADDR2 ADDR2 10 DATAx 11 (write) data1 12 12 R/W LSTRB Figure A-17. Example 2b: Emulation Expanded Mode Ò Write with 1 Stretch Cycle MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1256
Appendix A Electrical Characteristics Table A-33. Example 2b: Emulation Expanded Mode Timing 50 MHz bus, VDD5=5.0V (EWAIT disabled) No.
PAGE 1257
Appendix A Electrical Characteristics A.7.3.5 External Tag Trigger Timing 1 ECLK ADDR ADDR DATAx DATA R/W 2 TAGHI/TAGLO 3 Figure A-18. External Trigger Timing Table A-34. External Tag Trigger Timing VDD35 = 5.0 V Characteristic (1) No. C - D Frequency of internal bus 1 D 2 D Symbol Min Max Unit fi D.C. 50.0 MHz Cycle time tcyc 20 ∞ ns TAGHI/TAGLO setup time tTS 10 — ns 3 D TAGHI/TAGLO hold time 1.
PAGE 1258
Appendix B Package Information Appendix B Package Information This section provides the physical dimensions of the packages. MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1259
Appendix B Package Information B.1 208 MAPBGA LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA M NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASEMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. K E DIM A A1 A2 b D E e S M X D X 0.
PAGE 1260
Appendix B Package Information 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 P J1 L M CL B V X 140X B1 VIEW Y 36 V1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.
PAGE 1261
Appendix B Package Information B.3 112-Pin LQFP Package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 57 29 F D 56 0.13 N S1 A S C2 VIEW AB θ2 0.050 0.10 T T L-M N 112X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5.
PAGE 1262
Appendix B Package Information B.4 80-Pin QFP Package L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- -C- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H SEATING PLANE N M G U T DATUM PLANE -H- R K W Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.
PAGE 1263
Appendix C PCB Layout Guidelines Appendix C PCB Layout Guidelines The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins . • Central point of the ground star should be the VSS3 pin. • Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
PAGE 1264
Appendix C PCB Layout Guidelines Table C-1.
PAGE 1265
Appendix C PCB Layout Guidelines Figure C-1. 144-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1266
Appendix C PCB Layout Guidelines Figure C-2. 112-Pin LQFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1267
Appendix C PCB Layout Guidelines Figure C-3. 80-Pin QFP Recommended PCB Layout (Loop Controlled Pierce Oscillator) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1268
Appendix D Derivative Differences Appendix D Derivative Differences D.1 Memory Sizes and Package Options S12XE - Family Table D-1.
PAGE 1269
Appendix D Derivative Differences Table D-2.
PAGE 1270
Appendix D Derivative Differences D.2 Pinout explanations: • Pinout compatibility is maintained throughout the device family • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output. . • For additional flexibility especially for the low pin count packages several I/O functions can be routed under software control to different pins. For details refer to the device overview section..
PAGE 1271
Appendix E Detailed Register Address Map Appendix E Detailed Register Address Map The following tables show the detailed register map of the S12XE-Family. NOTE Smaller derivatives within the S12XE-Family feature a subset of the listed modules. Refer to Appendix D Derivative Differences for more information about derivative device module subsets.
PAGE 1272
Appendix E Detailed Register Address Map 0x000E–0x000F External Bus Interface (S12XEBI) Map Address Name 0x000E EBICTL0 0x000F EBICTL1 Bit 7 R W R W Bit 6 ITHRS 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 0 EXSTR12 EXSTR11 EXSTR10 EXSTR02 EXSTR01 EXSTR00 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 2 Address Name 0x0010 GPAGE 0x0011 DIRECT 0x0012 Reserved 0x0013 MMCCTL1 0x0014 Reserved 0x0015 PPAGE 0x0016 RPAGE 0x0017 EPAGE
PAGE 1273
Appendix E Detailed Register Address Map 0x001E–0x001F Port Integration Module (PIM) Map 3 of 6 Address Name 0x001E IRQCR 0x001F Reserved R W R W Bit 7 Bit 6 IRQE IRQEN 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0020–0x0027 Debug Module (S12XDBG) Map Address Name Bit 7 Bit 6 Bit 5 R 0 ARM XGSBPE BDM DBGBRK W TRIG R TBF EXTF 0 0 0 SSF2 0x0021 DBGSR W R 0x0022 DBGTCR TSOURCE TRANGE TRCMOD W R 0 0 0 0 0x0023 DBGC2 CD
PAGE 1274
Appendix E Detailed Register Address Map 0x0030–0x0031 Reserved Register Space 0x0030 Reserved 0x0031 Reserved R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0032–0x0033 Port Integration Module (PIM) Map 4 of 6 Address Name 0x0032 PORTK 0x0033 DDRK R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 0x0034–0x003F Clock and Reset Generator (CRG) Map Address Name 0x0034 SYNR
PAGE 1275
Appendix E Detailed Register Address Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) Address Name 0x0040 TIOS 0x0041 CFORC 0x0042 OC7M 0x0043 OC7D 0x0044 TCNT (high) 0x0045 TCNT (low) 0x0046 TSCR1 0x0047 TTOV 0x0048 TCTL1 0x0049 TCTL2 0x004A TCTL3 0x004B TCTL4 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 TC0 (hi) 0x0051 TC0 (lo) 0x0052 TC1 (hi) 0x0053 TC1 (lo) 0x0054 TC2 (hi) 0x0055 TC2 (lo) Bit 7 R IOS7 W R 0 W F
PAGE 1276
Appendix E Detailed Register Address Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3) Address Name 0x0056 TC3 (hi) 0x0057 TC3 (lo) 0x0058 TC4 (hi) 0x0059 TC4 (lo) 0x005A TC5 (hi) 0x005B TC5 (lo) 0x005C TC6 (hi) 0x005D TC6 (lo) 0x005E TC7 (hi) 0x005F TC7 (lo) 0x0060 PACTL 0x0061 PAFLG 0x0062 PACN3 (hi) 0x0063 PACN2 (lo) 0x0064 PACN1 (hi) 0x0065 PACN0 (lo) 0x0066 MCCTL 0x0067 MCFLG 0x0068 ICPAR 0x0069 DLYCT 0x006A ICOVW 0x006B IC
PAGE 1277
Appendix E Detailed Register Address Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3) Address Name 0x006D TIMTST 0x006E PTPSR 0x006F PTMCPSR 0x0070 PBCTL 0x0071 PBFLG 0x0072 PA3H 0x0073 PA2H 0x0074 PA1H 0x0075 PA0H 0x0076 MCCNT (hi) 0x0077 MCCNT (lo) 0x0078 TC0H (hi) 0x0079 TC0H (lo) 0x007A TC1H (hi) 0x007B TC1H (lo) 0x007C TC2H (hi) 0x007D TC2H (lo) 0x007E TC3H (hi) 0x007F TC3H (lo) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
PAGE 1278
Appendix E Detailed Register Address Map 0x0080–0x00AF Analog-to-Digital Converter 12-bit 16-Channels (ATD1) Map (Sheet 1 of 3) Address Name 0x0080 ATD1CTL0 0x0081 ATD1CTL1 0x0082 ATD1CTL2 0x0083 ATD1CTL3 0x0084 ATD1CTL4 0x0085 ATD1CTL5 0x0086 ATD1STAT0 0x0087 Reserved 0x0088 ATD1CMPEH 0x0089 ATD1CMPEL 0x008A ATD1STAT2H 0x008B ATD1STATL 0x008C ATD1DIENH 0x008D ATD1DIENL 0x008E ATD1CMPHTH 0x008F ATD1CMPHTL 0x0090 ATD1DR0H 0x0091 ATD1DR0L 0x0092 ATD1DR1H 0x0093 ATD1DR1L
PAGE 1279
Appendix E Detailed Register Address Map 0x0080–0x00AF Analog-to-Digital Converter 12-bit 16-Channels (ATD1) Map (Sheet 2 of 3) Address Name 0x0096 ATD1DR3H 0x0097 ATD1DR3L 0x0098 ATD1DR4H 0x0099 ATD1DR4L 0x009A ATD1DR5H 0x009B ATD1DR5L 0x009C ATD1DR6H 0x009D ATD1DR6L 0x009E ATD1DR7H 0x009F ATD1DR7L 0x00A0 ATD1DR8H 0x00A1 ATD1DR8L 0x00A2 ATD1DR9H 0x00A3 ATD1DR9L 0x00A4 ATD1DR10H 0x00A5 ATD1DR10L 0x00A6 ATD1DR11H 0x00A7 ATD1DR11L 0x00A8 ATD1DR12H 0x00A9 ATD1DR12L 0x
PAGE 1280
Appendix E Detailed Register Address Map 0x0080–0x00AF Analog-to-Digital Converter 12-bit 16-Channels (ATD1) Map (Sheet 3 of 3) Address Name 0x00AC ATD1DR14H 0x00AD 0x00AE 0x00AF R W R ATD1DR14L W R ATD1DR15H W R ATD1DR15L W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1281
Appendix E Detailed Register Address Map 0x00B0–0x00B7 Inter IC Bus (IIC1) Map Address Name 0x00B0 IBAD 0x00B1 IBFD 0x00B2 IBCR 0x00B3 IBSR 0x00B4 IBDR 0x00B5 IBCR2 0x00B6 Reserved 0x00B7 Reserved R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBEN IBIE MS/SL TX/RX TXAK 0 TCF IAAS IBB 0 0 RSTA SRW D7 D6 D5 D4 D3 D2 D1 D0 GCEN ADTYPE 0 0 0 ADR10 AD
PAGE 1282
Appendix E Detailed Register Address Map 0x00C0–0x00C7 Asynchronous Serial Interface (SCI3) Map Address 0x00C0 0x00C1 0x00C2 0x00C0 Name Bit 7 R IREN W R SCI3BDL1 SBR7 W R LOOPS SCI3CR11 W R SCI3ASR1(2) RXEDGIF W SCI3BDH(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 BERRV BERRIF BKDIF BERRIE BKDIE BERRM1 BERRM0 BKDFE RE RWU SBK NF FE PF BRK13 TXDIR
PAGE 1283
Appendix E Detailed Register Address Map 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R IREN TNP1 TNP0 SBR12 SBR11 W R SBR7 SBR6 SBR5 SBR4 SBR3 0x00C9 SCI0BDL1 W R LOOPS SCISWAI RSRC M WAKE 0x00CA SCI0CR11 W R 0 0 0 0 RXEDGIF 0x00C8 SCI0ASR1(2) W R 0 0 0 0 RXEDGIE 0x00C9 SCI0ACR12 W R 0 0 0 0 0 0x00CA SCI0ACR22 W R 0x00CB SCI0CR2 TIE TCIE RIE ILIE TE W R TDRE TC RDRF IDLE OR 0x00CC SCI0SR1 W R 0 0 0x00CD SCI0SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x00C
PAGE 1284
Appendix E Detailed Register Address Map 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R 0 0 0x00D5 SCI1SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x00D6 SCI1DRH T8 W R R7 R6 R5 R4 R3 0x00D7 SCI1DRL W T7 T6 T5 T4 T3 1. Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero 2.
PAGE 1285
Appendix E Detailed Register Address Map 0x00E0–0x00E7 Inter IC Bus (IIC0) Map (continued) Address Name 0x00E5 IBCR2 0x00E6 Reserved 0x00E7 Reserved Bit 7 R W R W R W Bit 6 Bit 5 Bit 4 Bit 3 0 0 0 Bit 2 Bit 1 Bit 0 ADR10 ADR9 ADR8 GCEN ADTYPE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAGE 1286
Appendix E Detailed Register Address Map 0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map Address Name 0x00F8 SPI2CR1 0x00F9 SPI2CR2 0x00FA SPI2BR 0x00FB SPI2SR 0x00FC SPI2DRH 0x00FD SPI2DRL 0x00FE Reserved 0x00FF Reserved R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE MODFEN BIDIROE SPISWAI SPC0 SPR2 SPR1 SPR0 0 XFRW 0 0 0 0 SPPR2 SPPR1 SPPR0 SPIF 0 SPTEF MODF 0 0 0 0 R1
PAGE 1287
Appendix E Detailed Register Address Map 0x0100–0x0113 NVM Control Register (FTM) Map (continued) Address Name 0x010C ETAGHI 0x010D ETAGLO 0x010E FECCRHI 0x010F FECCRLO 0x0110 FOPT 0x0111 Reserved 0x0112 Reserved 0x0113 Reserved Bit 7 R ETAG15 W R ETAG7 W R ECCR15 W R ECCR7 W R NV7 W R 0 W R 0 W R 0 W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ETAG14 ETAG13 ETAG12 ETAG11 ETAG10 ETAG9 ETAG8 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 ECCR14 ECCR13 ECCR12 ECCR11 ECCR1
PAGE 1288
Appendix E Detailed Register Address Map 0x0114–0x011F Memory Protection Unit (MPU) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R WPF NEXF 0 0 0 0 SVSF AEF W R 0 ADDR[22:16] 0x0115 MPUASTAT0 W R ADDR[15:8] 0x0116 MPUASTAT1 W R ADDR[7:0] 0x0117 MPUASTAT2 W R 0 0 0 0 0 0 0 0 0x0118 Reserved W R 0 0 0 0 0x0119 MPUSEL SVSEN SEL[2:0] W R MSTR0 MSTR1 MSTR2 MSTR3 LOW_ADDR[22:19] 0x011A MPUDESC0(1) W R 0x011B MPUDESC11 LOW_ADDR[18:11] W R LOW_ADDR[10:3] 0x011C MPUDESC21 W R 0 0 WP NE
PAGE 1289
Appendix E Detailed Register Address Map 0x0120–0x012F Interrupt Module (S12XINT) Map (continued) Address Name 0x0128 INT_CFDATA0 0x0129 INT_CFDATA1 0x012A INT_CFDATA2 0x012B INT_CFDATA3 0x012C INT_CFDATA4 0x012D INT_CFDATA5 0x012E INT_CFDATA6 0x012F INT_CFDATA7 Bit 7 R W R W R W R W R W R W R W R W RQST RQST RQST RQST RQST RQST RQST RQST Bit 6 Bit 5 Bit 4 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 Bit 1 Bit 0 PRIOLVL[2:0] PRIOLVL
PAGE 1290
Appendix E Detailed Register Address Map 0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R IREN TNP1 TNP0 SBR12 SBR11 W R SBR7 SBR6 SBR5 SBR4 SBR3 0x0131 SCI4BDL1 W R LOOPS SCISWAI RSRC M WAKE 0x0132 SCI4CR11 W R 0 0 0 0 RXEDGIF 0x0130 SCI4ASR1(2) W R 0 0 0 0 RXEDGIE 0x0131 SCI4ACR12 W R 0 0 0 0 0 0x0132 SCI4ACR22 W R 0x0133 SCI4CR2 TIE TCIE RIE ILIE TE W R TDRE TC RDRF IDLE OR 0x0134 SCI4SR1 W R 0 0 0x0135 SCI4SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x01
PAGE 1291
Appendix E Detailed Register Address Map 0x0138–0x013F Asynchronous Serial Interface (SCI5) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BRK13 TXDIR 0 0 0 R2 T2 R1 T1 R0 T0 Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK R 0 0 0x013D SCI5SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x013E SCI5DRH T8 W R R7 R6 R5 R4 R3 0x013F SCI5DRL W T7 T6 T5 T4 T3 1. Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to zero 2.
PAGE 1292
Appendix E Detailed Register Address Map 0x0140–0x017F MSCAN (CAN0) Map (continued) Address Name 0x0154– CAN0IDMR0– 0x0157 CAN0IDMR3 0x0158– CAN0IDAR4– 0x015B CAN0IDAR7 0x015C CAN0IDMR4– – CAN0IDMR7 0x015F R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 R 0x0160– 0x016F CAN0RXFG 0x0170– 0x017F CAN0TXFG FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground R
PAGE 1293
Appendix E Detailed Register Address Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name 0xXX0x XX10 Extended ID CANxTIDR1 Standard ID 0xXX12 0xXX13 0xXX14 – 0xXX1B 0xXX1C 0xXX1D 0xXX1E 0xXX1F R W R W Extended ID R CANxTIDR2 W Standard ID R W Extended ID R CANxTIDR3 W Standard ID R W R CANxTDSR0– CANxTDSR7 W R W R CANxTTBPR W R CANxTTSRH W R CANxTTSRL W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 ID2
PAGE 1294
Appendix E Detailed Register Address Map 0x0180–0x01BF MSCAN (CAN1) Map (Sheet 1 of 2) Address Name 0x0180 CAN1CTL0 0x0181 CAN1CTL1 0x0182 CAN1BTR0 0x0183 CAN1BTR1 0x0184 CAN1RFLG 0x0185 CAN1RIER 0x0186 CAN1TFLG 0x0187 CAN1TIER 0x0188 CAN1TARQ 0x0189 CAN1TAAK 0x018A CAN1TBSEL 0x018B CAN1IDAC 0x018C Reserved 0x018D CAN1MISC 0x018E CAN1RXERR 0x018F CAN1TXERR 0x0190 CAN1IDAR0 0x0191 CAN1IDAR1 0x0192 CAN1IDAR2 0x0193 CAN1IDAR3 0x0194 CAN1IDMR0 0x0195 CAN1IDMR1 Bit
PAGE 1295
Appendix E Detailed Register Address Map 0x0180–0x01BF MSCAN (CAN1) Map (Sheet 2 of 2) Address Name 0x0196 CAN1IDMR2 0x0197 CAN1IDMR3 0x0198 CAN1IDAR4 0x0199 CAN1IDAR5 0x019A CAN1IDAR6 0x019B CAN1IDAR7 0x019C CAN1IDMR4 0x019D CAN1IDMR5 0x019E CAN1IDMR6 0x019F CAN1IDMR7 0x01A0– 0x01AF CAN1RXFG 0x01B0– 0x01BF CAN1TXFG R W R W R W R W R W R W R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AM7 AM6 AM5 AM4 AM3 AM2
PAGE 1296
Appendix E Detailed Register Address Map 0x01C0–0x01FF MSCAN (CAN2) Map (Sheet 2 of 3) Address Name 0x01C8 CAN2TARQ 0x01C9 CAN2TAAK 0x01CA CAN2TBSEL 0x01CB CAN2IDAC 0x01CC Reserved 0x01CD CAN2MISC 0x01CE CAN2RXERR 0x01CF CAN2TXERR 0x01D0 CAN2IDAR0 0x01D1 CAN2IDAR1 0x01D2 CAN2IDAR2 0x01D3 CAN2IDAR3 0x01D4 CAN2IDMR0 0x01D5 CAN2IDMR1 0x01D6 CAN2IDMR2 0x01D7 CAN2IDMR3 0x01D8 CAN2IDAR4 0x01D9 CAN2IDAR5 0x01DA CAN2IDAR6 0x01DB CAN2IDAR7 0x01DC CAN2IDMR4 0x01DD CAN2IDMR5
PAGE 1297
Appendix E Detailed Register Address Map 0x01C0–0x01FF MSCAN (CAN2) Map (Sheet 3 of 3) Address Name R 0x01DF CAN2IDMR7 W R 0x01E0– CAN2RXFG 0x01EF W R 0x01F0– CAN2TXFG 0x01FF W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1298
Appendix E Detailed Register Address Map 0x0200–0x023F MSCAN (CAN3) Address Name 0x0200 CAN3CTL0 0x0201 CAN3CTL1 0x0202 CAN3BTR0 0x0203 CAN3BTR1 0x0204 CAN3RFLG 0x0205 CAN3RIER 0x0206 CAN3TFLG 0x0207 CAN3TIER 0x0208 CAN3TARQ 0x0209 CAN3TAAK 0x020A CAN3TBSEL 0x020B CAN3IDAC 0x020C Reserved 0x020D CAN3MISC 0x020E CAN3RXERR 0x020F CAN3TXERR 0x0210 CAN3IDAR0 0x0211 CAN3IDAR1 0x0212 CAN3IDAR2 0x0213 CAN3IDAR3 0x0214 CAN3IDMR0 0x0215 CAN3IDMR1 Bit 7 Bit 6 R RXFRM W
PAGE 1299
Appendix E Detailed Register Address Map 0x0200–0x023F MSCAN (CAN3) (continued) Address Name 0x0216 CAN3IDMR2 0x0217 CAN3IDMR3 0x0218 CAN3IDAR4 0x0219 CAN3IDAR5 0x021A CAN3IDAR6 0x021B CAN3IDAR7 0x021C CAN3IDMR4 0x021D CAN3IDMR5 0x021E CAN3IDMR6 0x021F CAN3IDMR7 0x0220– 0x022F CAN3RXFG 0x0230– 0x023F CAN3TXFG R W R W R W R W R W R W R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AM7 AM6 AM5 AM4 AM3 AM2 AM1
PAGE 1300
Appendix E Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 6 (continued) Address Name 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 MODRR 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP R W R W R W R W R W R W R W R W R W R W R W R W R
PAGE 1301
Appendix E Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 6 (continued) Address Name 0x0260 PTH 0x0261 PTIH 0x0262 DDRH 0x0263 RDRH 0x0264 PERH 0x0265 PPSH 0x0266 PIEH 0x0267 PIFH 0x0268 PTJ 0x0269 PTIJ 0x026A DDRJ 0x026B RDRJ 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026f PIFJ 0x0270 PT0AD0 0x0271 PT1AD0 0x0272 DDR0AD0 0x0273 DDR1AD0 0x0274 RDR0AD0 0x0275 RDR1AD0 0x0276 PER0AD0 0x0277 PER1AD0 R W R W R W R W R W R W R W R W
PAGE 1302
Appendix E Detailed Register Address Map 0x0240–0x027F Port Integration Module (PIM) Map 5 of 6 (continued) Address Name 0x0278 PT0AD1 0x0279 PT1AD1 0x027A DDR0AD1 0x027B DDR1AD1 0x027C RDR0AD1 0x027D RDR1AD1 0x027E PER0AD1 0x027F PER1AD1 R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT0AD1 7 PT0AD1 6 PT0AD1 5 PT0AD1 4 PT0AD1 3 PT0AD1 2 PT0AD1 1 PT0AD1 0 PT1AD1 7 PT1AD1 6 PT1AD1 5 PT1AD1 4 PT1AD1 3 PT1AD1 2 PT1AD1 1 PT1AD1 0 DDR0A
PAGE 1303
Appendix E Detailed Register Address Map 0x0280–0x02BF MSCAN (CAN4) Map (continued) Address Name 0x028D CAN4MISC 0x028E CAN4RXERR 0x028F CAN4TXERR 0x0290 CAN4IDAR0 0x0291 CAN4IDAR1 0x0292 CAN4IDAR2 0x0293 CAN4IDAR3 0x0294 CAN4IDMR0 0x0295 CAN4IDMR1 0x0296 CAN4IDMR2 0x0297 CAN4IDMR3 0x0298 CAN4IDAR4 0x0299 CAN4IDAR5 0x029A CAN4IDAR6 0x029B CAN4IDAR7 0x029C CAN4IDMR4 0x029D CAN4IDMR5 0x029E CAN4IDMR6 0x029F CAN4IDMR7 0x02A0– 0x02AF CAN4RXFG 0x02B0– 0x02BF CAN4TXFG
PAGE 1304
Appendix E Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map Address Name 0x02C0 ATD0CTL0 0x02C1 ATD0CTL1 0x02C2 ATD0CTL2 0x02C3 ATD0CTL3 0x02C4 ATD0CTL4 0x02C5 ATD0CTL5 0x02C6 ATD0STAT0 0x02C7 Reserved 0x02C8 ATD0CMPEH 0x02C9 ATD0CMPEL 0x02CA ATD0STAT2H 0x02CB ATD0STAT2L 0x02CC ATD0DIENH 0x02CD ATD0DIENL 0x02CE ATD0CMPHTH 0x02CF ATD0CMPHTL 0x02D0 ATD0DR0H 0x02D1 ATD0DR0L 0x02D2 ATD0DR1H 0x02D3 ATD0DR1L 0x02D4 ATD0DR2
PAGE 1305
Appendix E Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map (continued) Address Name 0x02D6 ATD0DR3H 0x02D7 ATD0DR3L 0x02D8 ATD0DR4H 0x02D9 ATD0DR4L 0x02DA ATD0DR5H 0x02DB ATD0DR5L 0x02DC ATD0DR6H 0x02DD ATD0DR6L 0x02DE ATD0DR7H 0x02DF ATD0DR7L 0x02E0 ATD0DR8H 0x02E1 ATD0DR8L 0x02E2 ATD0DR9H 0x02E3 ATD0DR9L 0x02E4 ATD0DR10H 0x02E5 ATD0DR10L 0x02E6 ATD0DR11H 0x02E7 ATD0DR11L 0x02E8 ATD0DR12H 0x02E9 ATD0DR12L 0x02EA
PAGE 1306
Appendix E Detailed Register Address Map 0x02C0–0x02EF Analog-to-Digital Converter 12-Bit 16-Channel (ATD0) Map (continued) Address 0x02ED 0x02EE 0x02EF Name R ATD0DR14L W R ATD0DR15H W R ATD0DR15L W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1307
Appendix E Detailed Register Address Map 0x02F0–0x02F7 Voltage Regulator (VREG_3V3) Map Address Name 0x02F0 VREGHTCL 0x02F1 VREGCTRL 0x02F2 VREGAPICL 0x02F3 VREGAPITR 0x02F4 VREGAPIRH 0x02F5 VREGAPIRL 0x02F6 Reserved 0x02F7 VREGHTTR Bit 7 Bit 6 R 0 W R 0 W R APICLK W R APITR5 W R APIR15 W R APIR7 W R 0 W R HTOEN W 0 Bit 5 Bit 4 Bit 3 Bit 2 HTDS Bit 1 Bit 0 HTIE HTIF LVIE LVIF APIE APIF 0 0 VSEL VAE HTEN 0 0 0 0 LVDS 0 0 APIFES APIEA APIFE APITR4 APITR3 API
PAGE 1308
Appendix E Detailed Register Address Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map (Sheet 2 of 3) Address 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 0x0314 0x0315 0x0316 0x0317 0x0318 0x0319 0x031A 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 Name R PWMSCNTA W R PWMSCNTB W R PWMCNT0 W R PWMCNT1 W R PWMCNT2 W R PWMCNT3 W R PWMCNT4 W R PWMCNT5 W R PWMCNT6 W R PWMCNT7 W R PWMPER0 W R PWMPER1 W R PWMPER2 W R PWMPER3 W R PWMPER4 W R PWMPER5 W R PWMPER6 W R PWMPER7 W
PAGE 1309
Appendix E Detailed Register Address Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map (Sheet 3 of 3) Address Name 0x0321 PWMDTY5 0x0322 PWMDTY6 0x0323 PWMDTY7 0x0324 PWMSDN 0x0325 Reserved 0x0326 Reserved 0x0327 Reserved R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 PWM7IN PWMIE PWM7INL PWM7 ENA 0 0 0 PWM RSTRT 0 0 PWMIF 0 0 0 PW
PAGE 1310
Appendix E Detailed Register Address Map 0x00330–0x0337 Asynchronous Serial Interface (SCI6) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R 0 0 0x0335 SCI6SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x0336 SCI6DRH T8 W R R7 R6 R5 R4 R3 0x0337 SCI6DRL W T7 T6 T5 T4 T3 1. Those registers are accessible if the AMAP bit in the SCI6SR2 register is set to zero 2.
PAGE 1311
Appendix E Detailed Register Address Map 0x00338–0x033F Asynchronous Serial Interface (SCI7) Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 R IREN TNP1 TNP0 SBR12 SBR11 W R SBR7 SBR6 SBR5 SBR4 SBR3 0x0339 SCI7BDL1 W R LOOPS SCISWAI RSRC M WAKE 0x033A SCI7CR11 W R 0 0 0 0 RXEDGIF 0x0338 SCI7ASR1(2) W R 0 0 0 0 RXEDGIE 0x0339 SCI7ACR12 W R 0 0 0 0 0 0x033A SCI7ACR22 W R 0x033B SCI7CR2 TIE TCIE RIE ILIE TE W R TDRE TC RDRF IDLE OR 0x033C SCI7SR1 W R 0 0 0x033D SCI7SR2 AMAP TXPOL RXPOL W R R8 0 0 0 0x03
PAGE 1312
Appendix E Detailed Register Address Map 0x00340–0x0367 – Periodic Interrupt Timer (PIT) Map (Sheet 2 of 3) Address Name 0x0349 PITLD0 (lo) 0x034A PITCNT0 (hi) 0x034B PITCNT0 (lo) 0x034C PITLD1 (hi) 0x034D PITLD1 (lo) 0x034E PITCNT1 (hi) 0x034F PITCNT1 (lo) 0x0350 PITLD2 (hi) 0x0351 PITLD2 (lo) 0x0352 PITCNT2 (hi) 0x0353 PITCNT2 (lo) 0x0354 PITLD3 (hi) 0x0355 PITLD3 (lo) 0x0356 PITCNT3 (hi) 0x0357 PITCNT3 (lo) 0x0358 PITLD4 (hi) 0x0359 PITLD4 (lo) 0x035A PITCNT4 (hi) 0
PAGE 1313
Appendix E Detailed Register Address Map 0x00340–0x0367 – Periodic Interrupt Timer (PIT) Map (Sheet 3 of 3) Address Name 0x0360 PITLD6 (hi) 0x0361 PITLD6 (lo) 0x0362 PITCNT6 (hi) 0x0363 PITCNT6 (lo) 0x0364 PITLD7 (hi) 0x0365 PITLD7 (lo) 0x0366 PITCNT7 (hi) 0x0367 PITCNT7 (lo) Bit 7 R PLD15 W R PLD7 W R PCNT15 W R PCNT7 W R PLD15 W R PLD7 W R PCNT15 W R PCNT7 W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD6 PLD5 PLD4 PLD3 PLD2 PLD
PAGE 1314
Appendix E Detailed Register Address Map 0x0368–0x037F Port Integration Module (PIM) Map 6 of 6 Address Name 0x0368 PTR 0x0369 PTIR 0x036A DDRR 0x036B RDRR 0x036C PERR 0x036D PPSR 0x036E Reserved 0x036F PTRRR 0x0370 PTL 0x0371 PTIL 0x0372 DDRL 0x0373 RDRL 0x0374 PERL 0x0375 PPSL 0x0376 WOML 0x0377 PTLRR 0x0378 PTF 0x0379 PTIF 0x037A DDRF 0x037B RDRF 0x037C PERF Bit 7 R PTR7 W R PTIR7 W R DDRR7 W R RDRR7 W R PERR7 W R PPSR7 W R 0 W R PTRRR7 W R PTL7 W R PTIL7 W R
PAGE 1315
Appendix E Detailed Register Address Map 0x0368–0x037F Port Integration Module (PIM) Map 6 of 6 (continued) Address Name 0x037D PPSF 0x037E Reserved 0x037F PTFRR R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PPSF7 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0 0 0 0 0 0 0 0 0 0 0 PTFRR5 PTFRR4 PTFRR3 PTFRR2 PTFRR1 PTFRR0 MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1316
Appendix E Detailed Register Address Map 0x0380–0x03BF XGATE Map (Sheet 1 of 3) Address Name 0x0380 XGMCTL 0x0381 XGMCTL 0x0382 XGCHID 0x0383 XGCHPL 0x0384 Reserved 0x0385 XGISPSEL 0x0386 XGVBR 0x0387 XGVBR 0x0388 XGIF 0x0389 XGIF 0x038A XGIF 0x023B XGIF 0x023C XGIF 0x038D XGIF 0x038E XGIF 0x038F XGIF 0x0390 XGIF 0x0391 XGIF 0x0392 XGIF 0x0393 XGIF 0x0394 XGIF 0x0395 XGIF R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit
PAGE 1317
Appendix E Detailed Register Address Map 0x0380–0x03BF XGATE Map (Sheet 2 of 3) Address Name 0x0396 XGIF 0x0397 XGIF 0x0398 XGSWTM 0x0399 XGSWT 0x039A XGSEMM 0x039B XGSEM 0x039C Reserved 0x039D XGCCR 0x039E XGPC (hi) 0x039F XGPC (lo) 0x03A0 Reserved 0x03A1 Reserved 0x03A2 XGR1 (hi) 0x03A3 XGR1 (lo) 0x03A4 XGR2 (hi) 0x03A5 XGR2 (lo) 0x03A6 XGR3 (hi) 0x03A7 XGR3 (lo) 0x03A8 XGR4 (hi) 0x03A9 XGR4 (lo) 0x03AA XGR5 (hi) 0x03AB XGR5(lo) 0x03AC XGR6 (hi) Bit 7 R XGI
PAGE 1318
Appendix E Detailed Register Address Map 0x0380–0x03BF XGATE Map (Sheet 3 of 3) Address Name 0x03AD XGR6 (lo) 0x03AE XGR7 (hi) 0x03AF XGR7 (lo) 0x03B0– 0x03BF Reserved Bit 7 R W R W R W R W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 XGR6[7:0] XGR7[15:8] XGR7[7:0] 0 0 0 0 0 MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1319
Appendix E Detailed Register Address Map 0x03C0–0x03CF Reserved Address Name 0x03C0 -0x03CF Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x03D0–0x03FF Timer Module (TIM) Map (Sheet 1 of 2) Address Name 0x03D0 TIOS 0x03D1 CFORC 0x03D2 OC7M 0x03D3 OC7D 0x03D4 TCNTH 0x03D5 TCNTL 0x03D6 TSCR1 0x03D7 TTOV 0x03D8 TCTL1 0x03D9 TCTL2 0x03DA TCTL3 0x03DB TCTL4 0x03DC TIE 0x03DD TSCR2 0x03DE TFLG1 0x03DF TFLG2 0x03E0 TC0H 0x03E1
PAGE 1320
Appendix E Detailed Register Address Map 0x03D0–0x03FF Timer Module (TIM) Map (Sheet 2 of 2) Address Name 0x03E4 TC2H 0x03E5 TC2L 0x03E6 TC3H 0x03E7 TC3L 0x03E8 TC4H 0x03E9 TC4L 0x03EA TC5H 0x03EB TC5L 0x03EC TC6H 0x03ED TC6L 0x03EE TC7H 0x03EF TC7L 0x03F0 PACTL 0x03F1 PAFLG 0x03F2 PACNTH 0x03F3 PACNTL 0x03F4– 0x03FB Reserved 0x03FC OCPD 0x03FD Reserved 0x03FE PTPSR 0x03FF Reserved Bit 7 R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R
PAGE 1321
Appendix E Detailed Register Address Map 0x0400–0x07FF Reserved Address Name 0x0400– 0x07FF Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 MC9S12XE-Family Reference Manual Rev. 1.
PAGE 1322
Appendix F Ordering Information Appendix F Ordering Information Customers can choose between ordering either the mask-specific partnumber or the generic / maskindependent partnumber. Ordering the mask-specific partnumber enables the customer to specify which particular maskset they receive whereas ordering the generic maskset means that the currently preferred maskset (which may change over time) is shipped.
PAGE 1323
PAGE 1324
How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 or 480-768-2130 Europe, Middle East, and Africa: +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) Japan: Freescale Semiconductor Japan Ltd.