Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 173
2.3.100 Port L Routing Register (PTLRR)
This register configures the re-routing of SCI7, SCI6, SCI5, and SCI4 on alternative ports.
2.3.101 Port F Data Register (PTF)
Address 0x0377 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PTLRR7 PTLRR6 PTLRR5 PTLRR4
0000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-98. Port L Routing Register (PTLRR)
Table 2-95. Port L Routing Summary
Module PTLRR Related Pins
7654
TXD RXD
SCI7 0 x x x PH3 PH2
1 x x x PL7 PL6
SCI6 x 0 x x PH1 PH0
x 1 x x PL5 PL4
SCI5 x x 0 x PH7 PH6
x x 1 x PL3 PL2
SCI4 x x x 0 PH5 PH4
x x x 1 PL1 PL0
Address 0x0378 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PTF7 PTFT6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
W
Altern.
Function
(TXD3) (RXD3) (SCL0) (SDA0) (
CS3) (CS2) (CS1) (CS0)
Reset 00000000
Figure 2-99. Port F Data Register (PTF)