Datasheet

Chapter 3 Memory Mapping Control (S12XMMCV4)
MC9S12XE-Family Reference Manual Rev. 1.25
188 Freescale Semiconductor
3.1.1 Terminology
3.1.2 Features
The main features of this block are:
• Paging capability to support a global 8 Mbytes memory address space
• Bus arbitration between the masters CPU, BDM and XGATE
Table 3-2. Acronyms and Abbreviations
Logic level “1” Voltage that corresponds to Boolean true state
Logic level “0” Voltage that corresponds to Boolean false state
0x Represents hexadecimal number
x Represents logic level ’don’t care’
byte 8-bit data
word 16-bit data
local address based on the 64 KBytes Memory Space (16-bit address)
global address based on the 8 MBytes Memory Space (23-bit address)
Aligned address Address on even boundary
Mis-aligned address Address on odd boundary
Bus Clock System Clock. Refer to CRG Block Guide.
expanded modes
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
single-chip modes
Normal Single-Chip Mode
Special Single-Chip Mode
emulation modes
Emulation Single-Chip Mode
Emulation Expanded Mode
normal modes
Normal Single-Chip Mode
Normal Expanded Mode
special modes
Special Single-Chip Mode
Special Test Mode
NS Normal Single-Chip Mode
SS Special Single-Chip Mode
NX Normal Expanded Mode
ES Emulation Single-Chip Mode
EX Emulation Expanded Mode
ST Special Test Mode
Unimplemented areas Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
External Space Area which is accessible in the global address range 14_0000 to 3F_FFFF
external resource
Resources (Emulator, Application) connected to the MCU via the external bus on
expanded modes (Unimplemented areas and External Space)
PRR Port Replacement Registers
PRU Port Replacement Unit located on the emulator side
MCU MicroController Unit
NVM Non-volatile Memory; Flash EEPROM or ROM