Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 175
2.3.102 Port F Input Register (PTIF)
2.3.103 Port F Data Direction Register (DDRF)
Address 0x0379 Access: User read
(1)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-100. Port F Input Register (PTIF)
Table 2-97. PTIF Register Field Descriptions
Field Description
7-0
PTIF
Port F input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Address 0x037A Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
W
Reset 00000000
Figure 2-101. Port F Data Direction Register (DDRF)
Table 2-98. DDRF Register Field Descriptions
Field Description
7-0
DDRF
Port F data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.