Datasheet

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 667
17.3.0.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD0–1)
Read: Anytime
Write: Anytime
17.3.0.8 PIT Load Register 0 to 7 (PITLD0–7)
Table 17-7. PITTF Field Descriptions
Field Description
7:0
PTF[7:0]
PIT Time-out Flag Bits for Timer Channel 7:0 — PTF is set when the corresponding 16-bit timer modulus
down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. The flag can be
cleared by writing a one to the flag bit. Writing a zero has no effect. If flag clearing by writing a one and flag setting
happen in the same bus clock cycle, the flag remains set. The flag bits are cleared if the PIT module is disabled
or if the corresponding timer channel is disabled.
0 Time-out of the corresponding PIT channel has not yet occurred.
1 Time-out of the corresponding PIT channel has occurred.
Module Base + 0x0006
76543210
R
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0
W
Reset 0 0 0 00000
Figure 17-9. PIT Micro Timer Load Register 0 (PITMTLD0)
Module Base + 0x0007
76543210
R
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0
W
Reset 0 0 0 00000
Figure 17-10. PIT Micro Timer Load Register 1 (PITMTLD1)
Table 17-8. PITMTLD0–1 Field Descriptions
Field Description
7:0
PMTLD[7:0]
PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers.
Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down
to zero, the PMTLD register value will be loaded. The PFLMT bits in the PITCFLMT register can be used to
immediately update the count register with the new value if an immediate load is desired.
Module Base + 0x0008, 0x0009
15 14 13 12 11 10 9876543210
R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
Reset 0000000000000000
Figure 17-11. PIT Load Register 0 (PITLD0)