Datasheet

Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual Rev. 1.25
356 Freescale Semiconductor
10.2 External Signal Description
The XGATE module has no external pins.
10.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the XGATE module.
The memory map for the XGATE module is given below in Figure 10-2.The address listed for each register
is the sum of a base address and an address offset. The base address is defined at the SoC level and the
address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved
registers have no effect.
10.3.1 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bits and field functions follow the register
diagrams, in bit order.
Register
Name
1514131211109876543210
0x0000
XGMCTL
R00000000
XGE XGFRZ XGDBG XGSS
XG
FACT
0
XG
SWEF
XGIE
W
XGEM
XG
FRZM
XG
DBGM
XGSSM
XG
FACTM
XG
SWEFM
XGIEM
0x0002
XGCHID
R 0 XGCHID[6:0]
W
0x0003
XGCHPL
R 00000 XGCHPL[2:0]
W
0x0004
Reserved
R
W
0x0005
XGISPSEL
R 000000
XGISPSEL[1:0]
W
0x0006
XGISP74
R
XGISP74[15:1]
0
W
0x0006
XGISP31
R
XGISP31[15:1]
0
W
0x0006
XGVBR
R
XGVBR[15:1]
0
W
= Unimplemented or Reserved
Figure 10-2. XGATE Register Summary (Sheet 1 of 3)