Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)

MC9S12XE-Family Reference Manual Rev. 1.25

536 Freescale Semiconductor

14.3.2.2 Timer Compare Force Register (CFORC)

Read or write: Anytime but reads will always return 0x0000 (1 state is transient).

All bits reset to zero.

14.3.2.3 Output Compare 7 Mask Register (OC7M)

Read or write: Anytime

All bits reset to zero.

Module Base + 0x0001

76543210

R00000000

W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

Reset 00000000

Figure 14-4. Timer Compare Force Register (CFORC)

Table 14-3. CFORC Field Descriptions

Field Description

7:0

FOC[7:0]

Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set

causes the action which is programmed for output compare “x” to occur immediately. The action taken is the

same as if a successful comparison had just taken place with the TCx register except the interrupt ﬂag does not

get set.

Note: A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or A successful channel 7 output

compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the

same time as the successful output compare, then the forced output compare action will take precedence

and the interrupt ﬂag will not get set.

Module Base + 0x0002

76543210

OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

Reset 00000000

Figure 14-5. Output Compare 7 Mask Register (OC7M)