Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
106 Freescale Semiconductor
2.3.2 Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
0x0378
PTF
R
PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
W
0x0379
PTIF
R PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0
W
0x037A
DDRF
R
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
W
0x037B
RDRF
R
RDRF7 RDRF6 RDRF5 RDRF4 RDRF3 RDRF2 RDRF1 RDRF0
W
0x037C
PERF
R
PERF7 PERF6 PERF5 PERF4 PERF3 PERF2 PERF1 PERF0
W
0x037D
PPSF
R
PPSF7 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0
W
0x037E
Reserved
R00000000
W
0x037F
PTFRR
R0 0
PTFRR5 PTFRR4 PTFRR3 PTFRR2 PTFRR1 PTFRR0
W
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved