Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor 107

Table 2-3. Pin Conﬁguration Summary

NOTE

All register bits in this module are completely synchronous to internal

clocks during a register read.

DDR IO RDR PE PS

(1)

1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.

(2)

2. Applicable only on Port P, H, and J.

Function Pull Device Interrupt

0 x x 0 x 0 Input Disabled Disabled

0 x x 1 0 0 Input Pull Up Disabled

0 x x 1 1 0 Input Pull Down Disabled

0 x x 0 0 1 Input Disabled Falling edge

0 x x 0 1 1 Input Disabled Rising edge

0 x x 1 0 1 Input Pull Up Falling edge

0 x x 1 1 1 Input Pull Down Rising edge

1 0 0 x x 0 Output, full drive to 0 Disabled Disabled

1 1 0 x x 0 Output, full drive to 1 Disabled Disabled

1 0 1 x x 0 Output, reduced drive to 0 Disabled Disabled

1 1 1 x x 0 Output, reduced drive to 1 Disabled Disabled

1 0 0 x 0 1 Output, full drive to 0 Disabled Falling edge

1 1 0 x 1 1 Output, full drive to 1 Disabled Rising edge

1 0 1 x 0 1 Output, reduced drive to 0 Disabled Falling edge

1 1 1 x 1 1 Output, reduced drive to 1 Disabled Rising edge