Datasheet

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
MC9S12XE-Family Reference Manual Rev. 1.25
1072 Freescale Semiconductor
27.4.3 Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
27.4.3.1 Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to Section 27.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 27.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 27.3.2.7, “Flash
Status Register (FSTAT)”, and Section 27.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 27-27.
Table 27-79. Flash Interrupt Sources
Interrupt Source Interrupt Flag Local Enable
Global (CCR)
Mask
Flash Command Complete CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
Flash EEE Erase Error ERSERIF
(FERSTAT register)
ERSERIE
(FERCNFG register)
I Bit
Flash EEE Program Error PGMERIF
(FERSTAT register)
PGMERIE
(FERCNFG register)
I Bit
Flash EEE Protection Violation EPVIOLIF
(FERSTAT register)
EPVIOLIE
(FERCNFG register)
I Bit
Flash EEE Error Type 1 Violation ERSVIF1
(FERSTAT register)
ERSVIE1
(FERCNFG register)
I Bit
Flash EEE Error Type 0 Violation ERSVIF0
(FERSTAT register)
ERSVIE0
(FERCNFG register)
I Bit
ECC Double Bit Fault on Flash Read DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit