Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
112 Freescale Semiconductor
2.3.10 Port D Data Direction Register (DDRD)
Table 2-10. DDRC Register Field Descriptions
Field Description
7-0
DDRC
Port C Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
Address 0x0007 (PRR) Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
W
Reset 00000000
Figure 2-8. Port D Data Direction Register (DDRD)
Table 2-11. DDRD Register Field Descriptions
Field Description
7-0
DDRD
Port D Data Direction—
This register controls the data direction of pins 7 through 0.
When used with the external bus this function controls the data direction for the associated pins. In this case the data
direction bits will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.