Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 113
2.3.11 Port E Data Register (PORTE)
Address 0x0008 (PRR) Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
PE7 PE6 PE5 PE4 PE3 PE2
PE1 PE0
W
Altern.
Function
XCLKS
or
ECLKX2
MODB
or
TAGHI
MODA
or
RE
or
TAGLO
ECLK
EROMCTL
or
LSTRB
or
LDS
R
W
or
WE
IRQ XIRQ
Reset 000000—
(2)
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
—
2
= Unimplemented or Reserved
Figure 2-9. Port E Data Register (PORTE)
Table 2-12. PORTE Register Field Descriptions
Field Description
7-2
PE
Port E general purpose input/output data—Data Register
Port E bits 7 through 0 are associated with external bus control signals and interrupt inputs. These include mode
select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (
TAGHI, TAGLO),
Read/Write (R
W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS).
When not used with the alternative functions, Port E pins 7-2 can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
1
PE
Port E general purpose input data and interrupt—Data Register,
IRQ input.
This pin can be used as general purpose and
IRQ input.
0
PE
Port E general purpose input data and interrupt—Data Register, XIRQ input.
This pin can be used as general purpose and
XIRQ input.