Datasheet

Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2)
MC9S12XE-Family Reference Manual Rev. 1.25
1156 Freescale Semiconductor
29.3.2.5 Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 29-14. FECCRIX Field Descriptions
Field Description
2-0
ECCRIX[2:0]
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
being read. See Section 29.3.2.13, “Flash ECC Error Results Register (FECCR),” for more details.
Offset Module Base + 0x0004
76543210
R
CCIE
00
IGNSF
00
FDFD FSFD
W
Reset 00000000
= Unimplemented or Reserved
Figure 29-9. Flash Configuration Register (FCNFG)
Table 29-15. FCNFG Field Descriptions
Field Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 29.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 29.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated