Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 117
2.3.15 ECLK Control Register (ECLKCTL)
1
RDPB
Port B reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced independent of the function used on
the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
0
RDPA
Port A reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced independent of the function used on
the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Address 0x001C (PRR) Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
Reset
(2)
:
2. Reset values in emulation modes are identical to those of the target mode.
Mode
Depen-
dent
1000000
SS01000000
ES11000000
ST01000000
EX01000000
NS11000000
NX01000000
= Unimplemented or Reserved
Figure 2-13. ECLK Control Register (ECLKCTL)
Table 2-15. RDRIV Register Field Descriptions (continued)
Field Description