Datasheet

Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 1215
Table A-11. Module Configurations for Maximum Run Supply Current V
DD35
=5.5V
Table A-10. Module Configurations for Typical Run Supply Current V
DD35
=5V
Peripheral Configuration
S12XCPU 420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
XGATE XGATE fetches code from RAM, XGATE runs in an infinite loop, reading the Status and Flag
registers of CAN’s, SPI’s, SCI’s in sequence and doing some bit manipulation on the data
MSCAN Configured to loop-back mode using a bit rate of 500kbit/s
SPI Configured to master mode, continuously transmit data (0x55 or 0xAA) at 2Mbit/s
SCI Configured into loop mode, continuously transmit data (0x55) at speed of 19200 baud
IIC Operate in master mode and continuously transmit data (0x55 or 0xAA) at 100Kbit/s
PWM Configured to toggle its pins at the rate of 1kHz
ECT The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
ATD The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
PIT PIT is enabled, Micro-timer register 0 and 1 loaded with $0F and timer registers 0 to 3 are loaded
with $03/07/0F/1F.
RTI Enabled with RTI Control Register (RTICTL) set to $59
Overhead VREG supplying 1.8V from a 5V input voltage, core clock tree active, PLL on
Peripheral Configuration
S12XCPU 420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
XGATE XGATE fetches code from RAM, XGATE runs in an infinite loop, reading the Status and Flag
registers of CAN’s, SPI’s, SCI’s in sequence and doing some bit manipulation on the data
MSCAN Configured to loop-back mode using a bit rate of 1Mbit/s
SPI Configured to master mode, continuously transmit data (0x55 or 0xAA) at 4Mbit/s
SCI Configured into loop mode, continuously transmit data (0x55) at speed of 57600 baud
IIC Operate in master mode and continuously transmit data (0x55 or 0xAA) at 100Kbit/s
PWM Configured to toggle its pins at the rate of 40kHz
ECT The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
ATD The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
Overhead VREG supplying 1.8V from a 5V input voltage, PLL on