Datasheet
Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 1219
A.2 ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
A.2.1 ATD Operating Characteristics
The Table A-15 and Table A-16 show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
SSA
≤ V
RL
≤ V
IN
≤ V
RH
≤ V
DDA
.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-15. ATD Operating Characteristics
A.2.2 Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.2.2.1 Differential Reference Voltage
The accuracy is reduced if the differential reference voltage is less than 3.13V when using the ATD in the
3.3V range or if the differential reference voltage is less than 4.5V when using the ATD in the 5V range.
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 3.13V < V
DDA
< 5.5 V
Num C Rating Symbol Min Typ Max Unit
1 D Reference potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
—
—
V
DDA
/2
V
DDA
V
V
2 D Voltage difference V
DDX
to V
DDA
∆
VDDX
–2.35 0 0.1 V
3 D Voltage difference V
SSX
to V
SSA
∆
VSSX
–0.1 0 0.1 V
4 C Differential reference voltage V
RH
-V
RL
3.13 5.0 5.5 V
5 C ATD Clock Frequency (derived from bus clock via the
prescaler) f
ATDCLk
0.25 — 8.3 MHz
6
P ATD Clock Frequency in Stop mode (internal generated
temperature and voltage dependent clock, ICLK)
0.6 1 1.7 MHz
7 D ADC conversion in stop, recovery time
(1)
1. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
t
ATDSTPRC
V
— — 1.5 us
8D
ATD Conversion Period
(2)
12 bit resolution:
10 bit resolution:
8 bit resolution:
2. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
N
CONV12
N
CONV10
N
CONV8
20
19
17
—
—
—
42
41
39
ATD
clock
Cycles