Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
122 Freescale Semiconductor
2.3.22 Port T Input Register (PTIT)
2.3.23 Port T Data Direction Register (DDRT)
Address 0x0241 Access: User read
(1)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-20. Port T Input Register (PTIT)
Table 2-21. PTIT Register Field Descriptions
Field Description
7-0
PTIT
Port T input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Address 0x0242 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 00000000
Figure 2-21. Port T Data Direction Register (DDRT)
Table 2-22. DDRT Register Field Descriptions
Field Description
7-0
DDRT
Port T data direction—
This register controls the data direction of pins 7 through 0.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.