Datasheet

Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual Rev. 1.25
1236 Freescale Semiconductor
Figure A-4. MC9S12XE-Family Power Sequencing
During power sequencing V
DDA
can be powered up before V
DDR
, V
DDX
.
V
DDR
and V
DDX
must be powered up together adhering to the operating conditions differential.
V
RH
power up must follow V
DDA
to avoid current injection.
A.6 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.6.1 Startup
Table A-23 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) block description
A.6.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
Table A-23. Startup Characteristics
Conditions are shown in Table A-4unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 D Reset input pulse width, minimum input time PW
RSTL
2——t
osc
2 D Startup from reset t
RST
192 — 4000
(1)
1. This is the time between RESET deassertion and start of CPU code execution.
n
bus
3 D Wait recovery startup time t
WRS
— — 14 t
cyc
4 D Fast wakeup from STOP
(2)
2. Including voltage regulator startup; V
DD
/V
DDF
filter capacitors 220 nF, V
DD35
= 5 V, T= 25°C
t
fws
— 50 100 µs
V
DDR,
V
DDA
t
V
V
DDX
>= 0