Datasheet

Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 1237
A.6.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
DD35
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG flags register has not been set.
A.6.1.3 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.6.1.4 Stop Recovery
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t
fws
.
A.6.1.5 Pseudo Stop and Wait Recovery
The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both
modes. The controller can be woken up by internal or external interrupts. After t
wrs
the CPU starts fetching
the interrupt vector.