Datasheet
Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
142 Freescale Semiconductor
2.3.52 Port P Interrupt Flag Register (PIFP)
2.3.53 Port H Data Register (PTH)
Address 0x025F Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
Reset 00000000
Figure 2-50. Port P Interrupt Flag Register (PIFP)
Table 2-48. PPSP Register Field Descriptions
Field Description
7-0
PIFP
Port P interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSP register. To clear this flag, write logic level 1 to the corresponding bit in the PIFP register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
Address 0x0260 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
W
Altern.
Function
SS2 SCK2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1
TXD5 RXD5 TXD4 RXD4 TXD7 RXD7 TXD6 RXD6
Reset 00000000
Figure 2-51. Port H Data Register (PTH)