Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
148 Freescale Semiconductor
2.3.59 Port H Interrupt Enable Register (PIEH)
Read: Anytime.
2.3.60 Port H Interrupt Flag Register (PIFH)
Address 0x0266 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
W
Reset 00000000
Figure 2-57. Port H Interrupt Enable Register (PIEH)
Table 2-55. PPSP Register Field Descriptions
Field Description
7-0
PIEH
Port H interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Address 0x0267 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
W
Reset 00000000
Figure 2-58. Port H Interrupt Flag Register (PIFH)
Table 2-56. PPSP Register Field Descriptions
Field Description
7-0
PIFH
Port H interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSH register. To clear this flag, write logic level 1 to the corresponding bit in the PIFH register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.