Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
152 Freescale Semiconductor
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
2.3.64 Port J Reduced Drive Register (RDRJ)
1
DDRJ
Port J data direction—
This register controls the data direction of pin 1.
The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin
when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0
DDRJ
Port J data direction—
This register controls the data direction of pin 0.
The enabled SCI3 or
CS3 signal forces the I/O state to be an output. In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x026B Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
RDRJ7 RDRJ6 RDRJ5 RDRJ4 RDRJ3 RDRJ2 RDRJ1 RDRJ0
W
Reset 00000000
Figure 2-62. Port J Reduced Drive Register (RDRJ)
Table 2-60. RDRJ Register Field Descriptions
Field Description
7-0
RDRJ
Port J reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Table 2-59. DDRJ Register Field Descriptions (continued)
Field Description