Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 157
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR1AD0 register.
NOTE
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.73 Port AD0 Reduced Drive Register 0 (RDR0AD0)
Table 2-68. DDR1AD0 Register Field Descriptions
Field Description
7-0
DDR1AD0
Port AD0 data direction—
This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x0274 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00
W
Reset 00000000
Figure 2-71. Port AD0 Reduced Drive Register 0 (RDR0AD0)
Table 2-69. RDR0AD0 Register Field Descriptions
Field Description
7-0
RDR0AD0
Port AD0 reduced drive—Select reduced drive for Port AD0 outputs
This register configures the drive strength of Port AD0 output pins 15 through 8 as either full or reduced independent
of the function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.