Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
168 Freescale Semiconductor
2.3.93 Port L Data Register (PTL)
5
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC5 is available on PP5
0 TIMIOC5 is available on PR5
4
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC4 is available on PP4
0 TIMIOC4 is available on PR4
3
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC3 is available on PP3
0 TIMIOC3 is available on PR3
2
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC2 is available on PP2
0 TIMIOC2 is available on PR2
1
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC1 is available on PP1
0 TIMIOC1 is available on PR1
0
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC0 is available on PP0
0 TIMIOC0 is available on PR0
Address 0x0370 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PTL7 PTLT6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0
W
Altern.
Function
(TXD7) (RXD7) (TXD6) (RXD6) (TXD5) (RXD5) (TXD4) (RXD4)
Reset 00000000
Figure 2-91. Port L Data Register (PTL)
Table 2-87. PTR Routing Register Field Descriptions (continued)
Field Description