Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
172 Freescale Semiconductor
2.3.98 Port L Polarity Select Register (PPSL)
2.3.99 Port L Wired-Or Mode Register (WOML)
Address 0x0375 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
PPSL7 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0
W
Reset 00000000
Figure 2-96. Port L Polarity Select Register (PPSL)
Table 2-93. PPSL Register Field Descriptions
Field Description
7-0
PPSL
Port L pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
Address 0x0376 Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
76543210
R
WOML7 WOML6 WOML5 WOML4 WOML3 WOML2 WOML1 WOML0
W
Reset 00000000
Figure 2-97. Port L Wired-Or Mode Register (WOML)
Table 2-94. WOML Register Field Descriptions
Field Description
7-0
WOML
Port L wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or independent of the function used on the pins. If enabled the
output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of
several serial modules. These bits have no influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.