Datasheet

Chapter 2 Port Integration Module (S12XEPIMV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 179
2.4.2.1 Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (Figure 2-107).
2.4.2.2 Input register (PTIx)
This is a read-only register and always returns the buffered state of the pin (Figure 2-107).
2.4.2.3 Data direction register (DDRx)
This register defines whether the pin is used as an input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-107).
Table 2-103. Register availability per port
(1)
1. Each cell represents one register with individual configuration bits
Port Data Input
Data
Direction
Reduced
Drive
Pull
Enable
Polarity
Select
Wired-
Or Mode
Interrupt
Enable
Interrupt
Flag
Routing
Ayes-yesyesyes-----
Byes-yes -----
Cyes-yes -----
Dyes-yes -----
Eyes-yes -----
Kyes-yes -----
Tyesyesyesyesyesyes----
S yes yes yes yes yes yes yes - - yes
M yes yes yes yes yes yes yes - - yes
P yes yes yes yes yes yes - yes yes -
H yes yes yes yes yes yes - yes yes -
J yes yes yes yes yes yes - yes yes -
AD0yes-yesyesyes-----
AD1yes-yesyesyes-----
Ryesyesyesyesyesyes----
L yes yes yes yes yes yes yes - - yes
F yes yes yes yes yes yes - - - yes