Datasheet

Chapter 5 External Bus Interface (S12XEBIV4)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 247
5.3.2.2 External Bus Interface Control Register 1 (EBICTL1)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register allows programming of two independent values determining the amount of additional stretch
cycles for external accesses (wait states).
With two bits in S12X_MMC register MMCCTL0 for every individual
CSx line one of the two counter
options or the
EWAIT input is selected as stretch source. The chip select outputs can also be disabled to
free up the pins for alternative functions (Table 5-6). Refer also to S12X_MMC section for register bit
descriptions.
If
EWAIT input usage is selected in MMCCTL0 the minimum number of stretch cycles is 2 for accesses
to the related address range.
If configured respectively, stretch cycles are added as programmed or dependent on
EWAIT in normal
expanded mode and emulation expanded mode; function not available in all other operating modes.
00011 ADDR[2:1], UDS
::
10110 ADDR[21:1],
UDS
10111
:
11111
ADDR[22:1],
UDS
Module Base +0x000F (PRR)
76543210
R0
EXSTR12 EXSTR11 EXSTR10
0
EXSTR02 EXSTR01 EXSTR00
W
Reset 01110111
= Unimplemented or Reserved
Figure 5-4. External Bus Interface Control Register 1 (EBICTL1)
Table 5-6. Chip select function
CSxE1 CSxE0 Function
00
CSx disabled
01
CSx stretched with EXSTR0
10
CSx stretched with EXSTR1
11
CSx stretched with EWAIT
Table 5-5. External Address Bus Size
ASIZ[4:0] Available External Address Lines