Datasheet

Chapter 5 External Bus Interface (S12XEBIV4)
MC9S12XE-Family Reference Manual Rev. 1.25
248 Freescale Semiconductor
5.4 Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
5.4.1 Operating Modes and External Bus Properties
A summary of the external bus interface functions for each operating mode is shown in Table 5-9.
Table 5-7. EBICTL1 Field Descriptions
Field Description
6–4
EXSTR1[2:0]
External Access Stretch Option 1 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
stretch cycles on every access to the external address space as shown in Table 5-8.
2–0
EXSTR0[2:0]
External Access Stretch Option 0 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
stretch cycles on every access to the external address space as shown in Table 5-8.
Table 5-8. External Access Stretch Bit Definition
EXSTRx[2:0] Number of Stretch Cycles
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8
Table 5-9. Summary of Functions
Properties
(if Enabled)
Single-Chip Modes Expanded Modes
Normal
Single-Chip
Special
Single-Chip
Normal
Expanded
Emulation
Single-Chip
Emulation
Expanded
Special
Test
Timing Properties
PRR access
(1)
2 cycles
read internal
write internal
2 cycles
read internal
write internal
2 cycles
read internal
write internal
2 cycles
read external
write int & ext
2 cycles
read external
write int & ext
2 cycles
read internal
write internal
Internal access
visible externally
——
—
1 cycle 1 cycle 1 cycle
External
address access
and
unimplemented area
access
(2)
— — Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait
(3)
1 cycle Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait
3
1 cycle