Datasheet

Chapter 5 External Bus Interface (S12XEBIV4)
MC9S12XE-Family Reference Manual Rev. 1.25
252 Freescale Semiconductor
5.4.2.4.2 Write Access Timing
5.4.2.4.3 Read-Write-Read Access Timing
DATA[15:0] (external read) ... ? zzzzz... data 0 z ...
R
W ...111111...11...
Table 5-15. Write Access (1 Cycle)
Access #0 Access #1 Access #2
Bus cycle ->
...
123
...
ECLK phase ... high low high low high low ...
ADDR[22:20] / ACC[2:0] ...
addr 0
acc 0
addr 1
acc 1
addr 2
acc 2 ...
ADDR[19:16] / IQSTAT[3:0] ...
iqstat -1 iqstat 0 iqstat 1 ...
ADDR[15:0] / IVD[15:0] ...
? x x ...
DATA[15:0] (write) ...
? data 0 data 1 data 2 ...
R
W ...001111...
Table 5-16. Write Access (2 Cycles)
Access #0 Access #1
Bus cycle ->
...
123
...
ECLK phase ... high low high low high low ...
ADDR[22:20] / ACC[2:0] ...
addr 0
acc 0
addr 0
000
addr 1
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ...
iqstat-1 iqstat 0 0000 ...
ADDR[15:0] / IVD[15:0] ...
? xx...
DATA[15:0] (write) ...
? data 0 x ...
R
W ...000011...
Table 5-17. Write Access (n–1 Cycles)
Access #0 Access #1
Bus cycle ->
...
123
...
n
...
ECLK phase ... high low high low high low ... high low ...
ADDR[22:20] / ACC[2:0] ...
addr 0
acc 0
addr 0
000
addr 0
000 ...
addr 1
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ...
iqstat-1 iqstat 0 0000 ... 0000 ...
ADDR[15:0] / IVD[15:0] ...
? x x ... x ...
DATA[15:0] (write) ...
? data 0 x ...
R
W ...000000...11...
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle)
Access #0 Access #1 Access #2
Bus cycle ->
...
123
...
Table 5-14. Read Access (n–1 Cycles)