Datasheet

Chapter 5 External Bus Interface (S12XEBIV4)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 255
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce
LSTRB = ADDR0 = 1. This is summarized in Table 5-20.
Table 5-20. Access in Emulation Modes and Special Test Mode
Access RW LSTRB ADDR0
DATA[15:8] DATA[7:0]
I/O data(addr) I/O data(addr)
Word write of data on DATA[15:0] at an even and even+1
address
0 0 0 Out data(even) Out data(odd)
Byte write of data on DATA[7:0] at an odd address 0 0 1 In x Out data(odd)
Byte write of data on DATA[15:8] at an even address 0 1 0 Out data(odd) In x
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
0 1 1 Out data(odd+1) Out data(odd)
Word read of data on DATA[15:0] at an even and even+1
address
1 0 0 In data(even) In data(even+1)
Byte read of data on DATA[7:0] at an odd address 1 0 1 In x In data(odd)
Byte read of data on DATA[15:8] at an even address 1 1 0 In data(even) In x
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
1 1 1 In data(odd+1) In data(odd)