Datasheet

Chapter 6 Interrupt (S12XINTV2)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 265
6.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XINT module.
6.3.1 Module Memory Map
Table 6-3 gives an overview over all XINT module registers.
Table 6-3. XINT Memory Map
Address Use Access
0x0120 RESERVED —
0x0121 Interrupt Vector Base Register (IVBR) R/W
0x0122–0x0125 RESERVED —
0x0126 XGATE Interrupt Priority Configuration Register
(INT_XGPRIO)
R/W
0x0127 Interrupt Request Configuration Address Register
(INT_CFADDR)
R/W
0x0128 Interrupt Request Configuration Data Register 0
(INT_CFDATA0)
R/W
0x0129 Interrupt Request Configuration Data Register 1
(INT_CFDATA1)
R/W
0x012A Interrupt Request Configuration Data Register 2
(INT_CFDATA2
R/W
0x012B Interrupt Request Configuration Data Register 3
(INT_CFDATA3)
R/W
0x012C Interrupt Request Configuration Data Register 4
(INT_CFDATA4)
R/W
0x012D Interrupt Request Configuration Data Register 5
(INT_CFDATA5)
R/W
0x012E Interrupt Request Configuration Data Register 6
(INT_CFDATA6)
R/W
0x012F Interrupt Request Configuration Data Register 7
(INT_CFDATA7)
R/W