Datasheet

Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual Rev. 1.25
370 Freescale Semiconductor
10.3.1.12 XGATE Program Counter Register (XGPC)
The XGPC register (Figure 10-14) provides access to the RISC core’s program counter.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
10.3.1.13 XGATE Register 1 (XGR1)
The XGR1 register (Figure 10-15) provides access to the RISC core’s register 1.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Module Base +0x0001E
1514131211109876543210
R
XGPC
W
Reset 0000000000000000
Figure 10-14. XGATE Program Counter Register (XGPC)
Table 10-14. XGPC Field Descriptions
Field Description
15–0
XGPC[15:0]
Program Counter — The RISC core’s program counter
Module Base +0x00022
1514131211109876543210
R
XGR1
W
Reset 0000000000000000
Figure 10-15. XGATE Register 1 (XGR1)
Table 10-15. XGR1 Field Descriptions
Field Description
15–0
XGR1[15:0]
XGATE Register 1 — The RISC core’s register 1