Datasheet

Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 371
10.3.1.14 XGATE Register 2 (XGR2)
The XGR2 register (Figure 10-16) provides access to the RISC core’s register 2.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
10.3.1.15 XGATE Register 3 (XGR3)
The XGR3 register (Figure 10-17) provides access to the RISC core’s register 3.
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Module Base +0x00024
1514131211109876543210
R
XGR2
W
Reset 0000000000000000
Figure 10-16. XGATE Register 2 (XGR2)
Table 10-16. XGR2 Field Descriptions
Field Description
15–0
XGR2[15:0]
XGATE Register 2 — The RISC core’s register 2
Module Base +0x00026
1514131211109876543210
R
XGR3
W
Reset 0000000000000000
Figure 10-17. XGATE Register 3 (XGR3)
Table 10-17. XGR3 Field Descriptions
Field Description
15–0
XGR3[15:0]
XGATE Register 3 — The RISC core’s register 3