Datasheet

Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 453
Operation
RS1 – RS2 ⇒ RD
RD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8])
Subtracts two 16 bit values and stores the result in the destination register RD.
NOTE
When using immediate addressing mode (SUB RD, #IMM16), the V-flag
and the C-Flag of the first instruction (SUBL RD, #IMM16[7:0]) are not
considered by the second instruction (SUBH RD, #IMM16[15:8]).
⇒ Don’t rely on the V-Flag if RD - IMM16[7:0] < −2
15
.
⇒ Don’t rely on the C-Flag if RD < IMM16[7:0].
CCR Effects
Code and CPU Cycles
SUB
Subtract without Carry
SUB
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] &
RS2[15] & RD[15]
new
| RS1[15] & RS2[15] & RD[15]
new
Refer to SUBH instruction for #IMM16 operations.
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
new
| RS2[15] & RD[15]
new
Refer to SUBH instruction for #IMM16 operations.
Source Form
Address
Mode
Machine Code Cycles
SUB RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 0 0 P
SUB RD, #IMM16 IMM8 1 1 0 0 0 RD IMM16[7:0] P
IMM8 1 1 0 0 1 RD IMM16[15:8] P