Datasheet

Chapter 10 XGATE (S12XGATEV3)

MC9S12XE-Family Reference Manual Rev. 1.25

458 Freescale Semiconductor

Operation

~(RS1 ^ RS2) ⇒ RD

~(RD ^ IMM16)⇒ RD

(translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0])

Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination

Remark: Using R0 as a source registers will calculate the one’s complement of the other source register.

Using R0 as both source operands will ﬁll RD with $FFFF.

NOTE

When using immediate addressing mode (XNOR RD, #IMM16), the Z-ﬂag

of the ﬁrst instruction (XNORL RD, #IMM16[7:0]) is not considered by the

second instruction (XNORH RD, #IMM16[15:8]).

⇒ Don’t rely on the Z-Flag.

CCR Effects

Code and CPU Cycles

XNOR

Logical Exclusive NOR

XNOR

NZVC

∆∆0—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

Refer to XNORH instruction for #IMM16 operations.

V: 0; cleared.

C: Not affected.

Source Form

Address

Mode

Machine Code Cycles

XNOR RD, RS1, RS2 TRI 0 0 0 1 0 RD RS1 RS2 1 1 P

XNOR RD, #IMM16 IMM8 1 0 1 1 0 RD IMM16[7:0] P

IMM8 1 0 1 1 1 RD IMM16[15:8] P