Datasheet

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
MC9S12XE-Family Reference Manual Rev. 1.25
472 Freescale Semiconductor
11.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12XECRG.
11.3.1 Module Memory Map
Figure 11-2 gives an overview on all S12XECRG registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000 SYNR
R
VCOFRQ[1:0] SYNDIV[5:0]
W
0x0001 REFDV
R
REFFRQ[1:0] REFDIV[5:0]
W
0x0002 POSTDIV
R0 0 0
POSTDIV[4:0]
W
0x0003 CRGFLG
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF SCMIF
SCM
W
0x0004 CRGINT
R
RTIE
00
LOCKIE
00
SCMIE
0
W
0x0005 CLKSEL
R
PLLSEL PSTP
XCLKS 0
PLLWAI
0
RTIWAI COPWAI
W
0x0006 PLLCTL
R
CME PLLON FM1 FM0 FSTWKP PRE PCE SCME
W
0x0007 RTICTL
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x0008 COPCTL
R
WCOP RSBCK
000
CR2 CR1 CR0
W WRTMASK
0x0009 FORBYP
2
R0 0 0 000 0 0
W
0x000A CTCTL
2
R0 0 0 000 0 0
W
0x000B ARMCOP
R0 0 0 000 0 0
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2. FORBYP and CTCTL are intended for factory test purposes only.
= Unimplemented or Reserved
Figure 11-2. CRG Register Summary