Datasheet

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
MC9S12XE-Family Reference Manual Rev. 1.25
480 Freescale Semiconductor
11.3.2.8 S12XECRG RTI Control Register (RTICTL)
This register selects the timeout period for the Real Time Interrupt.
Read: Anytime
Write: Anytime
NOTE
A write to this register initializes the RTI counter.
Table 11-8. FM Amplitude selection
FM1 FM0
FM Amplitude /
f
VCO
Variation
0 0 FM off
01 ±1%
10 ±2%
11 ±4%
Module Base + 0x0007
76543210
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
Reset 0 0 0 00000
Figure 11-10. S12XECRG RTI Control Register (RTICTL)
Table 11-9. RTICTL Field Descriptions
Field Description
7
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 11-10
1 Decimal based divider value. See Table 11-11
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 11-
10 and Table 11-11.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 11-10 and Table 11-11 show all possible divide values selectable by the
RTICTL register. The source clock for the RTI is OSCCLK.
Table 11-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[3:0]
RTR[6:4] =
000
(OFF)
001
(2
10
)
010
(2
11
)
011
(2
12
)
100
(2
13
)
101
(2
14
)
110
(2
15
)
111
(2
16
)
0000 (÷1)
OFF
(1)
2
10
2
11
2
12
2
13
2
14
2
15
2
16