Datasheet

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 509
13.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
0001 AN1
0010 AN2
0011 AN3
0100 AN4
0101 AN5
0110 AN6
0111 AN7
1000 AN8
1001 AN9
1010 AN10
1011 AN11
1100 AN12
1101 AN13
1110 AN14
1111 AN15
1. If only AN0 should be converted use MULT=0.
Module Base + 0x0001
76543210
R
ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
Reset 0 0 1 01111
Figure 13-4. ATD Control Register 1 (ATDCTL1)
Table 13-4. ATDCTL1 Field Descriptions
Field Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-
0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 13-6.
6–5
SRES[1:0]
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 13-5 for
coding.
Table 13-3. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting