Datasheet

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 515
13.3.2.6 ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
Read: Anytime
Write: Anytime
Table 13-13. ATDCTL4 Field Descriptions
Field Description
7–5
SMP[2:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 13-14 lists the available sample time lengths.
4–0
PRS[4:0]
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
Refer to Device Specification for allowed frequency range of f
ATDCLK
.
Table 13-14. Sample Time Select
SMP2 SMP1 SMP0
Sample Time
in Number of
ATD Clock Cycles
000 4
001 6
010 8
011 10
100 12
101 16
110 20
111 24
Module Base + 0x0005
76543210
R0
SC SCAN MULT CD CC CB CA
W
Reset 0 0 0 00000
Figure 13-8. ATD Control Register 5 (ATDCTL5)
f
ATDCLK
f
BUS
2 PRS 1+()×
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