Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 541
Table 14-11. The OC7 and OCx event priority
Note: in Table 14-11,the IOS7 and IOSx should be set to 1
IOSx is the register TIOS bit x,
OC7Mx is the register OC7M bit x,
TCx is timer Input Capture/Output Compare register,
IOCx is channel x,
OMx/OLx is the register TCTL1/TCTL2,
OC7Dx is the register OC7D bit x.
IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value.
14.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Read or write: Anytime
All bits reset to zero.
OC7M7=0 OC7M7=1
OC7Mx=1 OC7Mx=0 OC7Mx=1 OC7Mx=0
TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx
IOCx=OC7Dx
IOC7=OM7/O
L7
IOCx=OC7Dx
+OMx/OLx
IOC7=OM7/O
L7
IOCx=OMx/OLx
IOC7=OM7/OL7
IOCx=OC7Dx
IOC7=OC7D7
IOCx=OC7Dx
+OMx/OLx
IOC7=OC7D7
IOCx=OMx/OLx
IOC7=OC7D7
Module Base + 0x000A
76543210
R
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
W
Reset 00000000
Figure 14-13. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
76543210
R
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
W
Reset 00000000
Figure 14-14. Timer Control Register 4 (TCTL4)