Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
542 Freescale Semiconductor
14.3.2.10 Timer Interrupt Enable Register (TIE)
Read or write: Anytime
All bits reset to zero.
The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register.
Table 14-12. TCTL3/TCTL4 Field Descriptions
Field Description
EDG[7:0]B
7, 5, 3, 1
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture
edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the
active edge for the 16-bit pulse accumulator PACB. See Table 14-13.
EDG[7:0]A
6, 4, 2, 0
Table 14-13. Edge Detector Circuit Configuration
EDGxB EDGxA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)
Module Base + 0x000C
76543210
R
C7I C6I C5I C4I C3I C2I C1I C0I
W
Reset 00000000
Figure 14-15. Timer Interrupt Enable Register (TIE)
Table 14-14. TIE Field Descriptions
Field Description
7:0
C[7:0]I
Input Capture/Output Compare “x” Interrupt Enable
0 The corresponding flag is disabled from causing a hardware interrupt.
1 The corresponding flag is enabled to cause an interrupt.