Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
546 Freescale Semiconductor
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”).
14.3.2.14 Timer Input Capture/Output Compare Registers 0–7
Table 14-18. TFLG2 Field Descriptions
Field Description
7
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
Module Base + 0x0010
15 14 13 12 11 10 9 8
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 14-20. Timer Input Capture/Output Compare Register 0 High (TC0)
Module Base + 0x0011
76543210
R
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 14-21. Timer Input Capture/Output Compare Register 0 Low (TC0)
Module Base + 0x0012
15 14 13 12 11 10 9 8
R
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 14-22. Timer Input Capture/Output Compare Register 1 High (TC1)