Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
550 Freescale Semiconductor
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4
PEDGE
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1). Refer to Table 14-20.
For PAMOD bit = 0 (event counter mode).
0 Falling edges on IC7 pin cause the count to be incremented
1 Rising edges on IC7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 IC7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on IC7
sets the PAIF flag.
1 IC7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on IC7 sets
the PAIF flag.
If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the
timer prescaler.
3:2
CLK[1:0]
Clock Select Bits — For the description of PACLK please refer to Figure 14-72.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input
clock to the timer counter. The change from one selected clock to the other happens immediately after these bits
are written. Refer to Table 14-21.
2
PAOVI
Pulse Accumulator A Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAOVF is set
0
PAI
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
Table 14-20. Pin Action
PAMOD PEDGE Pin Action
0 0 Falling edge
0 1 Rising edge
1 0 Divide by 64 clock enabled with pin high level
1 1 Divide by 64 clock enabled with pin low level
Table 14-21. Clock Selection
CLK1 CLK0 Clock Source
0 0 Use timer prescaler clock as timer counter clock
0 1 Use PACLK as input to timer counter clock
1 0 Use PACLK/256 as timer counter clock frequency
1 1 Use PACLK/65536 as timer counter clock frequency
Table 14-19. PACTL Field Descriptions (continued)
Field Description