Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 551
14.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”).
14.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
Module Base + 0x0021
76543210
R000000
PAOVF PAIF
W
Reset 00000000
= Unimplemented or Reserved
Figure 14-37. Pulse Accumulator A Flag Register (PAFLG)
Table 14-22. PAFLG Field Descriptions
Field Description
1
PAOVF
Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on IC3.
0
PAIF
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IC7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IC7 input pin triggers PAIF.
Module Base + 0x0022
76543210
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)
W
Reset 00000000
Figure 14-38. Pulse Accumulators Count Register 3 (PACN3)