Datasheet

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 559
14.3.2.25 Output Compare Pin Disconnect Register (OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
14.3.2.26 Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
Module Base + 0x002C
76543210
R
OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0
W
Reset 00000000
Figure 14-48. Output Compare Pin Disconnect Register (OCPD)
Table 14-32. OCPD Field Descriptions
Field Description
7:0
OCPD[7:0]
Output Compare Pin Disconnect Bits
0 Enables the timer channel IO port. Output Compare actions will occur on the channel pin. These bits do not
affect the input capture or pulse accumulator functions.
1
Disables the timer channel IO port. Output Compare actions will not affect on the channel pin; the output
compare flag will still be set on an Output Compare event.
Module Base + 0x002E
76543210
R
PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0
W
Reset 00000000
Figure 14-49. Precision Timer Prescaler Select Register (PTPSR)
Table 14-33. PTPSR Field Descriptions
Field Description
7:0
PTPS[7:0]
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
These are effective only when the PRNT bit of TSCR1 is set to 1. Table 14-34 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.