Datasheet

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MC9S12XE-Family Reference Manual Rev. 1.25
594 Freescale Semiconductor
Figure 15-10. IIC-Bus Transmission Signals
15.4.1.1 START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in Figure 15-10, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
Figure 15-11. Start and Stop Conditions
C
L
D
A
Start
Signal
Ack
Bit
12345678
MSB LSB
1 2 34 5 6 78
MSB LSB
No
C
L
D
A
1234567 8
MSB LSB
12 5 678
MSB LSB
Repeated
34
99
ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Calling Address Read/ Data Byte
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address Read/
Write
No
Ack
Bit
Read/
Write
SDA
SCL
START Condition STOP Condition