Datasheet

MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor 659
Chapter 17
Periodic Interrupt Timer (S12PIT24B8CV2)
17.1 Introduction
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to Figure 17-1 for a simplified block diagram.
17.1.1 Glossary
17.1.2 Features
The PIT includes these features:
• Eight timers implemented as modulus down-counters with independent time-out periods.
• Time-out periods selectable between 1 and 2
24
bus clock cycles. Time-out equals m*n bus clock
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
• Timers that can be enabled individually.
• Eight time-out interrupts.
• Eight time-out trigger output signals available to trigger peripheral modules.
• Start of timer channels can be aligned to each other.
17.1.3 Modes of Operation
Refer to the device overview for a detailed explanation of the chip modes.
Table 17-1. Revision History
Revision
Number
RevisionDate
Sections
Affected
Description of Changes
V01.00 28 Apr 2005 - Initial Release.
V01.01 05 Jul 2005 17.6/17-674 - Added application section.
- Removed table 1-1.
Acronyms and Abbreviations
PIT Periodic Interrupt Timer
ISR Interrupt Service Routine
CCR Condition Code Register
SoC System on Chip
micro time bases clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.