Datasheet

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
MC9S12XE-Family Reference Manual Rev. 1.25
666 Freescale Semiconductor
17.3.0.5 PIT Interrupt Enable Register (PITINTE)
Read: Anytime
Write: Anytime
17.3.0.6 PIT Time-Out Flag Register (PITTF)
Read: Anytime
Write: Anytime (write to clear)
Table 17-5. PITMUX Field Descriptions
Field Description
7:0
PMUX[7:0]
PIT Multiplex Bits for Timer Channel 7:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is immediately switched to the other
micro time base.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
Module Base + 0x0004
76543210
R
PINTE7 PINTE6 PINTE5 PINTE4 PINTE3 PINTE2 PINTE1 PINTE0
W
Reset 0 0 0 00000
Figure 17-7. PIT Interrupt Enable Register (PITINTE)
Table 17-6. PITINTE Field Descriptions
Field Description
7:0
PINTE[7:0]
PIT Time-out Interrupt Enable Bits for Timer Channel 7:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
Module Base + 0x0005
76543210
R
PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
W
Reset 0 0 0 00000
Figure 17-8. PIT Time-Out Flag Register (PITTF)